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参数资料
| 型号： | IDT723666L15PF8 |
| 厂商： | IDT, Integrated Device Technology Inc |
| 文件页数： | 8/39页 |
| 文件大小： | 0K |
| 描述： | IC FIFO SYNC 8192X36 128QFP |
| 标准包装： | 1,000 |
| 系列： | 7200 |
| 功能： | 同步 |
| 存储容量： | 288K（8K x 36） |
| 数据速率： | 67MHz |
| 访问时间： | 15ns |
| 电源电压： | 4.5 V ~ 5.5 V |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 128-LQFP |
| 供应商设备封装： | 128-TQFP（14x20） |
| 包装： | 带卷 (TR) |
| 其它名称： | 723666L15PF8 |
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16
IDT723656/723666/723676 CMOS TRIPLE BUS SyncFIFOTM WITH
BUS MATCHING 2,048 x 36 x 2, 4,096 x 36 x 2 and 8,192 x 36 x 2
COMMERCIALTEMPERATURERANGE
IDT723676 respectively. Note that a data word present in the FIFO output
register has been read from memory.
TwoLOW-to-HIGHtransitionsoftheAlmost-Fullflagsynchronizingclockare
required after a FIFO read for its Almost-Full flag to reflect the new level of fill.
Therefore,theAlmost-FullflagofaFIFOcontaining[2,048/4,096/8,192-(Y+1)]
or less words remains LOW if two cycles of its synchronizing clock have not
elapsed since the read that reduced the number of words in memory to [2,048/
4,096/8,192-(Y+1)]. An Almost-Full flag is set HIGH by the second LOW-to-
HIGH transition of its synchronizing clock after the FIFO read that reduces the
number of words in memory to [2,048/4,096/8,192-(Y+1)]. A LOW-to-HIGH
transition of an Almost-Full flag synchronizing clock begins the first synchroni-
zation cycle if it occurs at time tSKEW2 or greater after the read that reduces the
number of words in memory to [2,048/4,096/8,192-(Y+1)]. Otherwise, the
subsequent synchronizing clock cycle may be the first synchronization cycle
(see Figure 26 and 27).
MAILBOX REGISTERS
EachFIFOhasan18-bitbypassregisterallowingthepassageofcommand
andcontrolinformationfromPortAtoPortBorfromPortCtoPortAwithoutputting
itinqueue. TheMailboxSelect(MBA,MBB andMBC)inputschoosebetween
a mail register and a FIFO for a port data transfer operation. The usable width
of both the Mail1 and Mail2 registers matches the selected bus size for port
B and C.
WhensendingdatafromPortAtoPortBviatheMail1Register,thefollowing
isthecase: ALOW-to-HIGHtransitiononCLKAwritesdatatotheMail1Register
when a Port A write is selected by
CSA, W/RA, and ENA with MBA HIGH. If
theselectedPortBbussizeis18bits,thentheusablewidthoftheMail1Register
employs data lines A0-A17. (In this case, A18-A35 are don’t care inputs.) If
theselectedPortBbussizeis9bits,thentheusablewidthoftheMail1Register
employs data lines A0-A8. (In this case, A9-A35 are don’t care inputs.)
WhensendingdatafromPortCtoPortAviatheMail2Register,thefollowing
isthecase: ALOW-to-HIGHtransitiononCLKCwritesdatatotheMail2Register
when a Port C write is selected by WENC with MBC HIGH. If the selected Port
C bus size is 18 bits, then the usable width of the Mail2 Register employs data
lines C0-C17. If the selected Port C bus size is 9 bits, then the usable width of
the Mail2 Register employs data lines C0-C8. (In this case, C9-C17 are don’t
care inputs.)
Writing data to a mail register sets its corresponding flag (
MBF1 or MBF2)
LOW. AttemptedwritestoamailregisterareignoredwhilethemailflagisLOW.
When data outputs of a port are active, the data on the bus comes from the
FIFO output register when the port Mailbox select input is LOW and from the
mail register when the port mailbox select input is HIGH.
The Mail1 Register Flag (
MBF1)issetHIGHbyaLOW-to-HIGHtransition
on CLKB when a Port B read is selected by
CSB,andRENBwithMBBHIGH.
For an 18-bit bus size, 18 bits of mailbox data are placed on B0-B17. For the
9-bit bus size, 9 bits of mailbox data are placed on B0-B8. (In this case, B9-
B17 are indeterminate.)
The Mail2 Register Flag (
MBF2)issetHIGHbyaLOW-to-HIGHtransition
on CLKA when a Port A read is selected by
CSA, W/RA, and ENA with MBA
HIGH. The data in a mail register remains intact after it is read and changes
only when new data is written to the register. For an 18-bit bus size, 18 bits
ofmailboxdataappearon A18-A35. (Inthiscase,A0-A17areindeterminate.)
For a 9-bit bus size, 9 bits of mailbox data appear on A18-A26. (In this case,
A0-A17 and A27-A35 are indeterminate.)
The data in a mail register remains intact after it is read and changes only
whennewdataiswrittentotheregister. TheEndianSelectfeaturehasnoeffect
on mailbox data.
NotethatMBCmustbeHIGHduringMasterReset(until
FFA/IRAand FFC/
IRC go HIGH. MBA and MBB are don't care inputs during Master Reset. For
mail register and mail register flag timing diagrams, see Figure 28 and 29.
BUS SIZING
Port B may be configured in either an 18-bit word or a 9-bit byte format for
data read from FIFO1. Port C may be configured in either an 18-bit word or
a 9-bit byte format for data written to FIFO2. The bus size can be selected
independently for Ports B and C. The level applied to the Port B Size Select
(SIZEB) input determines the Port B bus size and the level applied to the Port
C Size Select (SIZEC) input determines the Port C bus size. These levels
should be static throughout FIFO operation. Both bus size selections are
implementedatthecompletionofMasterReset,bythetimetheFull/InputReady
flag is set HIGH, as shown in Figure 2 and 3.
Two different methods for sequencing data transfer are available for Ports
BandCregardlessofwhetherthebussizeselectionisbyte-orword-size. They
arereferredtoasBig-Endian(mostsignificantbytefirst)andLittle-Endian(least
significant byte first). The level applied to the Big-Endian Select (BE) input
during the LOW-to-HIGH transition of
MRS1 and MRS2 selects the endian
methodthatwillbeactiveduringFIFOoperation. Thisselectionappliestoboth
portsBandC. TheendianmethodisimplementedatthecompletionofMaster
Reset, by the time the Full/Input Ready flag is set HIGH, as shown in Figure
2 and 3 (see Endian Selection section).
Only 36-bit long word data is written to or read from the two FIFO memories
on these devices. Bus-Matching operations are done after data is read from
the FIFO1 RAM (Port B) and before data is written to the FIFO2 RAM (Port
C). The Endian select operations are not available when transferring data via
mailbox registers. Furthermore, both the word- and byte-size bus selections
limit the width of the data bus that can be used for mail register operations. In
this case, only those byte lanes belonging to the selected word- or byte-size
buscancarrymailboxdata. Theremainingdataoutputswillbeindeterminate.
Theremainingdatainputswillbedon’tcareinputs. Forexample,whenaword-
size bus is selected on Port B, then mailbox data can be transmitted only from
A0-A17 to B0-B17. When a byte-size bus is selected on Port B, then mailbox
data can be transmitted only from A0-A8 to B0-B8. Similarly, when a word-
size bus is selected on Port C, then mailbox data can be transmitted only from
C0-C17toA18-A35. Whenabyte-sizebusisselectedonPortC,thenmailbox
data can be transmitted only from C0-C8 to A18-A26.
BUS-MATCHING FIFO1 READS
DataisreadfromtheFIFO1RAMin36-bitlongwordincrements. SincePort
B can have a byte or word size, only the first one or two bytes appear on the
selectedportionoftheFIFO1outputregister,withtherestofthelongwordstored
in auxiliary registers. In this case, subsequent FIFO1 reads output the rest of
the long word to the FIFO1 output register in the order shown by Figure 2.
When reading data from FIFO1 in byte format, the unused B9-B17 outputs
areindeterminate.
BUS-MATCHING FIFO2 WRITES
DataiswrittentotheFIFO2RAMin36-bitlongwordincrements. Datawritten
toFIFO2withabyteorwordbussizestorestheinitialbytesorwordsinauxiliary
registers. The CLKC rising edge that writes the fourth byte or the second word
of long word to FIFO2 also stores the entire long word in the FIFO2 memory.
The bytes are arranged in the manner shown in Figure 3.
When writing data to FIFO2 in byte format, the unused C9-C17 inputs are
don't care inputs.
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参数描述 |
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| IDT723672L12PF | 功能描述:IC FIFO SYNC 16384X36 120QFP RoHS:否 类别:集成电路 (IC) >> 逻辑 - FIFO 系列:7200 标准包装:15 系列:74F 功能:异步 存储容量:256（64 x 4） 数据速率:- 访问时间:- 电源电压:4.5 V ~ 5.5 V 工作温度:0°C ~ 70°C 安装类型:通孔 封装/外壳:24-DIP（0.300"，7.62mm） 供应商设备封装:24-PDIP 包装:管件 其它名称:74F433 |
| IDT723672L12PF8 | 功能描述:IC FIFO SYNC 16384X36 120QFP RoHS:否 类别:集成电路 (IC) >> 逻辑 - FIFO 系列:7200 标准包装:15 系列:74F 功能:异步 存储容量:256（64 x 4） 数据速率:- 访问时间:- 电源电压:4.5 V ~ 5.5 V 工作温度:0°C ~ 70°C 安装类型:通孔 封装/外壳:24-DIP（0.300"，7.62mm） 供应商设备封装:24-PDIP 包装:管件 其它名称:74F433 |
| IDT723672L12PQF | 功能描述:IC FIFO SYNC 16384X36 132QFP RoHS:否 类别:集成电路 (IC) >> 逻辑 - FIFO 系列:7200 标准包装:15 系列:74F 功能:异步 存储容量:256（64 x 4） 数据速率:- 访问时间:- 电源电压:4.5 V ~ 5.5 V 工作温度:0°C ~ 70°C 安装类型:通孔 封装/外壳:24-DIP（0.300"，7.62mm） 供应商设备封装:24-PDIP 包装:管件 其它名称:74F433 |
| IDT723672L15PF | 功能描述:IC FIFO SYNC 16384X36 120QFP RoHS:否 类别:集成电路 (IC) >> 逻辑 - FIFO 系列:7200 标准包装:15 系列:74F 功能:异步 存储容量:256（64 x 4） 数据速率:- 访问时间:- 电源电压:4.5 V ~ 5.5 V 工作温度:0°C ~ 70°C 安装类型:通孔 封装/外壳:24-DIP（0.300"，7.62mm） 供应商设备封装:24-PDIP 包装:管件 其它名称:74F433 |
| IDT723672L15PF8 | 功能描述:IC FIFO SYNC 16384X36 120QFP RoHS:否 类别:集成电路 (IC) >> 逻辑 - FIFO 系列:7200 标准包装:15 系列:74F 功能:异步 存储容量:256（64 x 4） 数据速率:- 访问时间:- 电源电压:4.5 V ~ 5.5 V 工作温度:0°C ~ 70°C 安装类型:通孔 封装/外壳:24-DIP（0.300"，7.62mm） 供应商设备封装:24-PDIP 包装:管件 其它名称:74F433 |
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