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参数资料
| 型号： | IDT723673L15PF8 |
| 厂商： | IDT, Integrated Device Technology Inc |
| 文件页数： | 6/29页 |
| 文件大小： | 0K |
| 描述： | IC FIFO SYNC 8192X36 128QFP |
| 标准包装： | 1,000 |
| 系列： | 7200 |
| 功能： | 同步 |
| 存储容量： | 288K（8K x 36） |
| 数据速率： | 67MHz |
| 访问时间： | 15ns |
| 电源电压： | 4.5 V ~ 5.5 V |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 128-LQFP |
| 供应商设备封装： | 128-TQFP（14x20） |
| 包装： | 带卷 (TR) |
| 其它名称： | 723673L15PF8 |
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14
COMMERCIALTEMPERATURERANGE
IDT723653/723663/723673 CMOS SyncFIFOTM WITH BUS-MATCHING
2,048 x 36 x 2, 4,096 x 36 x 2 and 8,192 x 36 x 2
transition of an Almost-Full flag synchronizing clock begins the first synchroni-
zation cycle if it occurs at time tSKEW2 or greater after the read that reduces the
number of words in memory to [2,048/4,096/8,192-(Y+1)]. Otherwise, the
subsequent synchronizing clock cycle may be the first synchronization cycle
(see Figure 16).
MAILBOX REGISTERS
Two 36-bit bypass registers are on the IDT723653/723663/723673 to pass
command and control information between Port A and Port B without putting it
in queue. The Mailbox select (MBA, MBB) inputs choose between a mail
register and a FIFO for a port data transfer operation. The usable width of both
the Mail1 and Mail2 Registers matches the selected bus size for Port B.
A LOW-to-HIGH transition on CLKA writes data to the Mail1 Register when
a Port A write is selected by
CSA, W/RA, and ENA with MBA HIGH. If the
selectedPortBbussizeis36bits,theusablewidthoftheMail1Registeremploys
datalinesA0-A35.IftheselectedPortBbussizeis18bits,thentheusablewidth
of the Mail1 Register employs data lines A0-A17. (In this case, A18-A35 are
don’t care inputs.) If the selected Port B bus size is 9 bits, then the usable width
oftheMail1RegisteremploysdatalinesA0-A8.(Inthiscase,A9-A35aredon’t
care inputs.)
ALOW-to-HIGHtransitiononCLKBwritesB0-B35datatotheMail2Register
when a Port B write is selected by
CSB, W/RB, and ENB with MBB HIGH. If
the selected Port B bus size is 36 bits, the usable width of the Mail2 employs
datalinesB0-B35.IftheselectedPortBbussizeis18bits,thentheusablewidth
of the Mail2 Register employs data lines B0-B17. (In this case, B18-B35 are
don’t care inputs.) If the selected Port B bus size is 9 bits, then the usable width
oftheMail2RegisteremploysdatalinesB0-B8.(Inthiscase,B9-B35aredon’t
care inputs.)
Writing data to a mail register sets its corresponding flag (
MBF1 or MBF2)
LOW.AttemptedwritestoamailregisterareignoredwhilethemailflagisLOW.
When data outputs of a port are active, the data on the bus comes from the
FIFO output register when the port Mailbox select input is LOW and from the
mail register when the port Mailbox select input is HIGH.
The Mail1 Register Flag (
MBF1)issetHIGHbyaLOW-to-HIGHtransition
on CLKB when a Port B read is selected by
CSB, W/RB, and ENB with MBB
HIGH. For a 36-bit bus size, 36 bits of mailbox data are placed on B0-B35. For
an 18-bit bus size, 18 bits of mailbox data are placed on B0-B17. (In this case,
B18-B35 are indeterminate.) For a 9-bit bus size, 9 bits of mailbox data are
placed on B0-B8. (In this case, B9-B35 are indeterminate.)
The Mail2 Register Flag (
MBF2)issetHIGHbyaLOW-to-HIGHtransition
on CLKA when a Port A read is selected by
CSA, W/RA, and ENA with MBA
HIGH.
For a 36-bit bus size, 36 bits of mailbox data are placed on A0-A35. For an
18-bitbussize,18bitsofmailboxdataareplacedonA0-A17.(Inthiscase,A18-
A35 are indeterminate.) For a 9-bit bus size, 9 bits of mailbox data are placed
on A0-A8. (In this case, A9-A35 are indeterminate.)
Thedatainamailregisterremainsintactafteritisreadandchangesonlywhen
new data is written to the register. The Endian select feature has no effect on
mailboxdata.Formailregisterandmailregisterflagtimingdiagrams,seeFigure
17 and 18.
BUS SIZING
The Port B bus can be configured in a 36-bit long word, 18-bit word, or 9-
bit byte format for data read from the FIFO. The levels applied to the Port B Bus
Sizeselect(SIZE)andtheBus-Matchselect(BM)determinethePortBbussize.
These levels should be static throughout FIFO operation. Both bus size
selectionsareimplementedatthecompletionofReset,bythetimetheFull/Input
Ready flag is set HIGH, as shown in Figure 2.
Two different methods for sequencing data transfer are available for Port B
when the bus size selection is either byte-or word-size. They are referred to
asBig-Endian(mostsignificantbytefirst)andLittle-Endian(leastsignificantbyte
first). The level applied to the Big-Endian select (BE) input during the LOW-to-
HIGHtransitionof
RS1selectstheendianmethodthatwillbeactiveduringFIFO
operation. BE is a don’t care input when the bus size selected for Port B is long
word.TheendianmethodisimplementedatthecompletionofReset,bythetime
the Full/Input Ready flag is set HIGH, as shown in Figure 2.
Only 36-bit long word data is written to or read from the FIFO memory on the
IDT723653/723663/723673. Bus-matching operations are done after data is
read from the FIFO RAM. These bus-matching operations are not available
when transferring data via mailbox registers. Furthermore, both the word- and
byte-size bus selections limit the width of the data bus that can be used for mail
registeroperations.Inthiscase,onlythosebytelanesbelongingtotheselected
word- or byte-size bus can carry mailbox data. The remaining data outputs will
be indeterminate. The remaining data inputs will be don’t care inputs. For
example,whenaword-sizebusisselected,thenmailboxdatacanbetransmitted
only between A0-A17 and B0-B17. When a byte-size bus is selected, then
mailboxdatacanbetransmittedonlybetweenA0-A8andB0-B8.(SeeFigures
17 and 18).
BUS-MATCHING FIFO READS
DataisreadfromtheFIFORAMin36-bitlongwordincrements.Ifalongword
bussizeisimplemented,theentirelongwordimmediatelyshiftstotheFIFOoutput
register. If byte or word size is implemented on Port B, only the first one or two
bytes appear on the selected portion of the FIFO output register, with the rest
of the long word stored in auxiliary registers. In this case, subsequent FIFO
reads output the rest of the long word to the FIFO output register in the order
shown by Figure 2.
When reading data from FIFO in byte or word format, the unused B0-B35
outputsareindeterminate.
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| IDT723674L12PF | 功能描述:IC FIFO SYNC 16384X36 128QFP RoHS:否 类别:集成电路 (IC) >> 逻辑 - FIFO 系列:7200 标准包装:15 系列:74F 功能:异步 存储容量:256（64 x 4） 数据速率:- 访问时间:- 电源电压:4.5 V ~ 5.5 V 工作温度:0°C ~ 70°C 安装类型:通孔 封装/外壳:24-DIP（0.300"，7.62mm） 供应商设备封装:24-PDIP 包装:管件 其它名称:74F433 |
| IDT723674L12PF8 | 功能描述:IC FIFO SYNC 16384X36 128QFP RoHS:否 类别:集成电路 (IC) >> 逻辑 - FIFO 系列:7200 标准包装:15 系列:74F 功能:异步 存储容量:256（64 x 4） 数据速率:- 访问时间:- 电源电压:4.5 V ~ 5.5 V 工作温度:0°C ~ 70°C 安装类型:通孔 封装/外壳:24-DIP（0.300"，7.62mm） 供应商设备封装:24-PDIP 包装:管件 其它名称:74F433 |
| IDT723674L15PF | 功能描述:IC FIFO SYNC 16384X36 128QFP RoHS:否 类别:集成电路 (IC) >> 逻辑 - FIFO 系列:7200 标准包装:15 系列:74F 功能:异步 存储容量:256（64 x 4） 数据速率:- 访问时间:- 电源电压:4.5 V ~ 5.5 V 工作温度:0°C ~ 70°C 安装类型:通孔 封装/外壳:24-DIP（0.300"，7.62mm） 供应商设备封装:24-PDIP 包装:管件 其它名称:74F433 |
| IDT723674L15PF8 | 功能描述:IC FIFO SYNC 16384X36 128QFP RoHS:否 类别:集成电路 (IC) >> 逻辑 - FIFO 系列:7200 标准包装:15 系列:74F 功能:异步 存储容量:256（64 x 4） 数据速率:- 访问时间:- 电源电压:4.5 V ~ 5.5 V 工作温度:0°C ~ 70°C 安装类型:通孔 封装/外壳:24-DIP（0.300"，7.62mm） 供应商设备封装:24-PDIP 包装:管件 其它名称:74F433 |
| IDT723676L12PF | 功能描述:IC FIFO SYNC 16384X36 128QFP RoHS:否 类别:集成电路 (IC) >> 逻辑 - FIFO 系列:7200 标准包装:15 系列:74F 功能:异步 存储容量:256（64 x 4） 数据速率:- 访问时间:- 电源电压:4.5 V ~ 5.5 V 工作温度:0°C ~ 70°C 安装类型:通孔 封装/外壳:24-DIP（0.300"，7.62mm） 供应商设备封装:24-PDIP 包装:管件 其它名称:74F433 |
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