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参数资料
| 型号： | IDT723676L15PF |
| 厂商： | IDT, Integrated Device Technology Inc |
| 文件页数： | 6/39页 |
| 文件大小： | 0K |
| 描述： | IC FIFO SYNC 16384X36 128QFP |
| 标准包装： | 36 |
| 系列： | 7200 |
| 功能： | 同步 |
| 存储容量： | 576K（16K x 36） |
| 数据速率： | 67MHz |
| 访问时间： | 15ns |
| 电源电压： | 4.5 V ~ 5.5 V |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 128-LQFP |
| 供应商设备封装： | 128-TQFP（14x20） |
| 包装： | 托盘 |
| 其它名称： | 723676L15PF |
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14
IDT723656/723666/723676 CMOS TRIPLE BUS SyncFIFOTM WITH
BUS MATCHING 2,048 x 36 x 2, 4,096 x 36 x 2 and 8,192 x 36 x 2
COMMERCIALTEMPERATURERANGE
TABLE 5 —
—
— FIFO1 FLAG OPERATION (IDT Standard and FWFT modes)
TABLE 6 —
—
— FIFO2 FLAG OPERATION (IDT Standard and FWFT modes)
Synchronized
Number of Words in FIFO Memory(1,2)
to CLKB
to CLKA
IDT723656(3)
IDT723666(3)
IDT723676(3)
EFB/ORB
AEB
AFA
FFA/IRA
00
0
L
H
1 to X1
H
L
H
(X1+1) to [2,048-(Y1+1)]
(X1+1) to [4,096-(Y1+1)]
(X1+1) to [8,192-(Y1+1)]
H
(2,048-Y1) to 2,047
(4,096-Y1) to 4,095
(8,192-Y1) to 8,191
H
L
H
2,048
4,096
8,192
H
L
NOTES:
1. When a word loaded to an empty FIFO is shifted to the output register, its previous FIFO memory location is free.
2. Data in the output register does not count as a "word in FIFO memory". Since in FWFT mode, the first word written to an empty FIFO goes unrequested to the output register (no read operation
necessary), it is not included in the FIFO memory count.
3. X1 is the almost-empty offset for FIFO1 used by
AEB. Y1 is the almost-full offset for FIFO1 used by AFA. Both X1 and Y1 are selected during a FIFO1 reset or port A programming.
4. The ORB and IRA functions are active during FWFT mode; the
EFB and FFA functions are active in IDT Standard mode.
NOTES:
1. When a word loaded to an empty FIFO is shifted to the output register, its previous FIFO memory location is free.
2. Data in the output register does not count as a "word in FIFO memory". Since in FWFT mode, the first word written to an empty FIFO goes unrequested to the output register (no read operation
necessary), it is not included in the FIFO memory count.
3. X2 is the almost-empty offset for FIFO2 used by
AEA. Y2 is the almost-full offset for FIFO2 used by AFC. Both X2 and Y2 are selected during a FIFO2 reset or port A programming.
4. The ORA and IRC functions are active during FWFT mode; the
EFA and FFC functions are active in IDT Standard mode.
Synchronized
Number of Words in FIFO Memory
(1,2)
to CLKA
to CLKC
IDT723656(3)
IDT723666(3)
IDT723676(3)
EFA/ORA
AEA
AFC
FFC/IRC
00
0
L
H
1 to X2
H
L
H
(X2+1) to [2,048-(Y2+1)]
(X2+1) to [4,096-(Y2+1)]
(X2+1) to [8,192-(Y2+1)]
H
(2,048-Y2) to 2,047
(4,096-Y2) to 4,095
(8,192-Y2) to 8,191
H
L
H
2,048
4,096
8,192
H
L
Data is read from FIFO1 to the B0-B17 outputs by a LOW-to-HIGH
transition of CLKB when
CSBisLOW,RENBisHIGH,MBBisLOWandEFB/
ORB is HIGH (see Table 3). FIFO reads on Port B are independent of any
concurrent Port A and Port C operations.
Data is loaded into FIFO2 from the C0-C17 inputs on a LOW-to-HIGH
transition of CLKC when WENB is HIGH, MBC is LOW, and
FFC/IRCisHIGH
(see Table 4). FIFO writes on Port C are independent of any concurrent Port
A and Port B operation.
The setup and hold time constraints for
CSAandW/RAwithregardtoCLKA
as well as
CSB with regard to CLKB are only for enabling write and read
operations and are not related to high-impedance control of the data outputs.
If ENA is LOW during a clock cycle, either
CSA or W/RA may change states
during the setup and hold time window of the cycle. This is also true for
CSB
when RENB is LOW.
WhenoperatingtheFIFOinFWFTmodeandtheOutputReadyflagisLOW,
the next word written is automatically sent to the FIFO’s output register by the
LOW-to-HIGHtransitionoftheportclockthatsetstheOutputReadyflagHIGH.
When the Output Ready flag is HIGH, subsequent data is clocked to the output
registersonlywhenareadisselectedusing
CSA,W/RA,ENAandMBAatPort
A or using
CSB, RENB and MBB at Port B.
WhenoperatingtheFIFOinIDTStandardmode,thefirstwordwillcausethe
EmptyFlagtochangestateonthesecondLOW-to-HIGHtransitionoftheRead
Clock. Thedatawordwillnotbeautomaticallysenttotheoutputregister. Instead,
data residing in the FIFO’s memory array is clocked to the output register only
when a read is selected using
CSA, W/RA, ENA and MBA at Port A or using
CSB, RENB and MBB at Port B. Relevant write and read timing diagrams for
Port A can be found in Figure 10 and 15. Relevant read and write timing
diagrams for Port B and Port C, together with Bus-Matching and Endian select
operation, can be found in Figure 11 to 14.
LOOPBACK (
LOOP)
ALoopbackfunctionisprovidedonPortAandisselectedbysettingthe
LOOP
pinLOW.WhentheLoopfeatureisselected,thedataoutputfromFIFO2willbe
directed to the data input of FIFO1. If Loop is selected and Port A is set-up for
write operation via the W/RA pin being HIGH, then data output from FIFO2 will
bewrittentoFIFO1,oneveryLOW-to-HIGHtransitionofCLKA,provided
CSA
is LOW and ENA is HIGH. However, FIFO2 data output will not be placed on
the output Port A (A0-A35). If Port A is set-up for read operation via the W/RA
pinbeingLOW,thendataoutputfromFIFO2willbewrittenintoFIFO1onevery
LOW-to-HIGHtransitionofCLKA,provided
CSAisLOWandENAisHIGH. Also
FIFO2datawillbeoutputtoPortA(A0-A35). Whenthe
LOOPpinisHIGHthen
Port A operates in the normal manner. Refer to Table 2 for the input set-up of
the Loop feature.
The Loop operation will continue to happen provided that FIFO1 is not full
and FIFO2 is not empty. If during a Loop sequence FIFO1 becomes full then
any data that continues to be read out from FIFO2 will only be placed on the
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