参数资料
型号: IDT72403L10SO
厂商: IDT, Integrated Device Technology Inc
文件页数: 1/9页
文件大小: 0K
描述: IC FIFO PAR 64X4 10NS 16-SOIC
标准包装: 46
系列: 7200
功能: 异步
存储容量: 256(64 x 4)
数据速率: 10MHz
访问时间: 10ns
电源电压: 4.5 V ~ 5.5 V
工作温度: 0°C ~ 70°C
安装类型: 表面贴装
封装/外壳: 16-SOIC(0.295",7.50mm 宽)
供应商设备封装: 16-SOIC
包装: 管件
其它名称: 72403L10SO
JUNE 2012
2012 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.
DSC-2747/13
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc.
FAST is a trademark of National Semiconductor, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
1
IDT72401
IDT72403
CMOSPARALLELFIFO
64 x 4
FEATURES:
First-ln/First-Out Dual-Port memory
64 x 4 organization (IDT72401/72403)
RAM-based FIFO with low falI-through time
Low-power consumption
— Active: 175mW (typ.)
Maximum shift rate — 45MHz
High data output drive capability
Asynchronous and simultaneous read and write
Fully expandable by bit width
Fully expandable by word depth
IDT72403 have Output Enable pin to enable output data
High-speed data communications applications
High-performance CMOS technology
Available in CERDIP, plastic DIP and SOIC
Military product compliant to MlL-STD-883, Class B
Standard Military Drawing #5962-86846 and
5962-89523 is listed on this function.
Green parts available, see ordering information
DESCRIPTION:
The IDT72401 and IDT72403 are asynchronous high-performance
First-ln/First-Outmemoriesorganized64wordsby4bits. TheIDT72403 also
hasanOutputEnable(OE)pin.TheFlFOsaccept4-bit dataatthedatainput
(D0-D3). The stored data stack up on a first-in/first-out basis.
AShiftOut(SO)signalcausesthedataatthenexttolastwordtobeshifted
totheoutputwhileallotherdatashiftsdownonelocationinthestack.TheInput
Ready (IR) signal acts like a flag to indicate when the input is ready for new
data (IR = HIGH) or to signal when the FIFO is full (IR = LOW). The IR signal
canalsobeusedtocascademultipledevicestogether.TheOutputReady(OR)
signal is a flag to indicate that the output remains valid data (OR = HIGH) or
to indicate that the FIFO is empty (OR = LOW). The OR can also be used to
cascademultipledevicestogether.
WidthexpansionisaccomplishedbylogicallyANDingtheIRandORsignals
toformcompositesignals.
Depthexpansionisaccomplishedbytyingthedatainputsofonedeviceto
the data outputs of the previous device. The IR pin of the receiving device is
connected to the SO pin of the sending device and the OR pin of the sending
device is connected to the Shift In (SI) pin of the receiving device.
Readingandwritingoperationsarecompletelyasynchronousallowingthe
FIFO to be used as a buffer between two digital machines of widely varying
operatingfrequencies.The45MHzspeedmakestheseFlFOsidealforhigh-
speed communicationandcontrollerapplications.
MilitarygradeproductismanufacturedincompliancewiththeofMIL-STD-
883, Class B.
FUNCTIONAL BLOCK DIAGRAM
WRITE POINTER
INPUT
CONTROL
LOGIC
2747 drw01
SI
DATA IN
MASTER
RESET
WRITE MULTIPLEXER
MEMORY
ARRAY
READ POINTER
READ MULTIPLEXER
IR
D0-3
MR
OUTPUT
ENABLE
DATA IN
MASTER
RESET
SO
OR
Q0-3
OE
(IDT72403 only)
相关PDF资料
PDF描述
MS3106A12S-3SW CONN PLUG 2POS STRAIGHT W/SCKT
MS3106R22-22S CONN PLUG 4POS STRAIGHT W/SCKT
IDT72401L10SO IC FIFO PAR 64X4 10NS 16-SOIC
VE-253-IU-F1 CONVERTER MOD DC/DC 24V 200W
VE-252-IU-F4 CONVERTER MOD DC/DC 15V 200W
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