参数资料
型号: IDT72821L15PFI
厂商: IDT, Integrated Device Technology Inc
文件页数: 4/16页
文件大小: 0K
描述: IC FIFO SYNC 1KX9 15NS 64QFP
标准包装: 90
系列: 7200
功能: 同步
存储容量: 9K(1K x 9)
数据速率: 67MHz
访问时间: 15ns
电源电压: 4.5 V ~ 5.5 V
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 64-LQFP
供应商设备封装: 64-TQFP(14x14)
包装: 托盘
其它名称: 72821L15PFI
12
IDT72801/728211/72821/72831/72841/72851 DUAL CMOS SyncFIFOTM
DUAL 256 x 9, DUAL 512 x 9, DUAL 1K x 9, DUAL 2K x 9, DUAL 4K x 9, DUAL 8K x 9
COMMERCIAL AND INDUSTRIAL
TEMPERATURERANGES
MARCH 2013
Figure 10. Programmable Full Flag Timing
NOTES:
1. m = PAF offset.
2. (256-m) words for the IDT72801; (512-m) words the IDT72811; (1,024-m) words for the IDT72821; (2,048-m) words for the IDT72831; (4,096-m) words for the IDT72841; or (8,192-m)
words for the IDT72851.
3. tSKEW2 is the minimum time between a rising RCLKA (RCLKB) edge and a rising WCLKA (WCLKB) edge for PAFA (PAFB) to change during that clock cycle. If the time between the
rising edge of RCLKA (RCLKB) and the rising edge of WCLKA (WCLKB) is less than tSKEW2, then PAFA (PAFB) may not change state until the next WCLKA (WCLKB) rising edge.
4. If a write is performed on this rising edge of the write clock, there will be Full - (m-1) words in FIFO A (B) when PAFA (PAFB) goes LOW.
tENS
tENH
tENS
tENH
tENS
tENH
WCLKA
(WCLKB)
WENA1
(
WENB1)
WENA2 (WENB2)
(If Applicable)
PAFA
(
PAFB)
RCLKA (RCLKB)
RENA1, RENA2
(
RENB1, RENB2)
(4)
(1)
tPAF
Full - (m+1) words in FIFO
Full - m words in FIFO
(2)
tCLKH
tCLKL
tSKEW2
(3)
tPAF
3034 drw 11
WCLKA (WCLKB)
WENA1
(
WENB1)
WENA2 (WENB2)
(If Applicable)
PAEA,
PAEB
RCLKA (RCLKB)
RENA1, RENA2
(
RENB1, RENB2)
tENS
tENH
tENS
tENH
tSKEW2
(2)
tENS
tENH
tPAE
(3)
(1)
n words in FIFO
n+1 words in FIFO
tCLKH
tCLKL
3034 drw 12
NOTES:
1. n = PAE offset.
2. tSKEW2 is the minimum time between a rising WCLKA (WCLKB) edge and a rising RCLKA (RCLKB) edge for PAEA (PAEB) to change during that clock cycle. If the time between the
rising edge of WCLKA (WCLKB) and the rising edge of RCLKA (RCLKB) is less than tSKEW2, then PAEA (PAEB) may not change state until the next RCLKA (RCLKB) rising edge.
3. If a read is performed on this rising edge of the read clock, there will be Empty + (n-1) words in FIFO A (B) when PAEA (PAEB) goes LOW.
Figure 11. Programmable Empty Flag Timing
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