参数资料
型号: IDT72T1885L5BB
厂商: IDT, Integrated Device Technology Inc
文件页数: 11/55页
文件大小: 0K
描述: IC FIFO 32768X18 2.5V 5NS 144BGA
标准包装: 1
系列: 72T
功能: 异步,双端口
存储容量: 589K(32K x 18)
数据速率: 10MHz
访问时间: 5ns
电源电压: 2.375 V ~ 2.625 V
工作温度: 0°C ~ 70°C
安装类型: 表面贴装
封装/外壳: 144-BGA
供应商设备封装: 144-PBGA(13x13)
包装: 托盘
其它名称: 72T1885L5BB
19
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
IDT72T1845/55/65/75/85/95/105/115/125 2.5V TeraSync 18-BIT/9-BIT FIFO 2Kx18/4Kx9, 4Kx18/
8Kx9, 8Kx18/16Kx9, 16Kx18/32Kx9, 32Kx18/64Kx9, 64Kx18/128Kx9, 128Kx18/256Kx9, 256Kx18/512Kx9, 512Kx18/1Mx9
FEBRUARY 10, 2009
Figure 3. Programmable Flag Offset Programming Sequence
WCLK
RCLK
X
XX
X
XX
LD
0
X
1
0
WEN
0
1
0
X
1
REN
1
0
1
X
0
1
1X
SEN
1
X
0
No Operation
Write Memory
Read Memory
No Operation
Parallel write to registers:
Serial shift into registers:
Ending with Full Offset (MSB)
I
DT72T1845,
IDT72T1855
IDT72T1865,
IDT72T1875
IDT72T1885,
IDT72T1895
IDT72T18105,
IDT72T18115
IDT72T18125
24 bits for the IDT72T1845
26 bits for the IDT72T1855
28 bits for the IDT72T1865
30 bits for the IDT72T1875
32 bits for the IDT72T1885
34 bits for the IDT72T1895
36 bits for the IDT72T18105
38 bits for the IDT72T18115
40 bits for the IDT72T18125
1 bit for each rising SCLK edge
Starting with Empty Offset (LSB)
Serial shift into registers:
Ending with Full Offset (MSB)
22 bits for the IDT72T1845
24 bits for the IDT72T1855
26 bits for the IDT72T1865
28 bits for the IDT72T1875
30 bits for the IDT72T1885
32 bits for the IDT72T1895
34 bits for the IDT72T18105
36 bits for the IDT72T18115
38 bits for the IDT72T18125
1 bit for each rising SCLK edge
Starting with Empty Offset (LSB)
x9 to x9 Mode
All Other Modes
5909 drw06
x18 input
Empty Offset
Full Offset
x18 input
(72T18105/115/125)
Empty Offset (LSB)
Empty Offset (MSB)
Full Offset (LSB)
Full Offset (MSB)
x9 input
Empty Offset (LSB)
Empty Offset (MSB)
Full Offset (LSB)
Full Offset (MSB)
x9 input
(72T1895/105/115/125)
Empty Offset (LSB)
Empty Offset
Empty Offset (MSB)
Full Offset (LSB)
Full Offset
Full Offset (MSB)
Parallel read from registers:
x18 input
Empty Offset
Full Offset
x18 input
(72T18105/115/125)
Empty Offset (LSB)
Empty Offset (MSB)
Full Offset (LSB)
Full Offset (MSB)
x9 input
Empty Offset (LSB)
Empty Offset (MSB)
Full Offset (LSB)
Full Offset (MSB)
x9 input
(72T1895/105/115/125)
Empty Offset (LSB)
Empty Offset
Empty Offset (MSB)
Full Offset (LSB)
Full Offset
Full Offset (MSB)
NOTES:
1. The programming method can only be selected at Master Reset.
2. Parallel reading of the offset registers is always permitted regardless of which programming method has been selected.
3. The programming sequence applies to both IDT Standard and FWFT modes.
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