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| 型号： | IDT72V2105L10PFG8 |
| 厂商： | IDT, Integrated Device Technology Inc |
| 文件页数： | 20/26页 |
| 文件大小： | 0K |
| 描述： | IC FIFO SUPERSYNCII 10NS 64-TQFP |
| 标准包装： | 750 |
| 系列： | 72V |
| 功能： | 同步 |
| 存储容量： | 4.7Mb（262k x 18） |
| 访问时间： | 10ns |
| 电源电压： | 3 V ~ 3.6 V |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 64-LQFP |
| 供应商设备封装： | 64-TQFP（14x14） |
| 包装： | 带卷 (TR) |
| 其它名称： | 72V2105L10PFG8 |
3
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
IDT72V295/72V2105 3.3V HIGH DENSITY CMOS
SUPERSYNC FIFOTM 131,072 x 18, 262,144 x 18
Figure 1. Block Diagram of Single 131,072 x 18 and 262,144 x 18 Synchronous FIFO
In IDT Standard mode, the first word written to an empty FIFO will not
appear on the data output lines unless a specific read operation is
performed. A read operation, which consists of activating
RENand enabling
a rising RCLK edge, will shift the word from internal memory to the data
output lines.
In FWFT mode, the first word written to an empty FIFO is clocked directly
to the data output lines after three transitions of the RCLK signal. A
REN
does not have to be asserted for accessing the first word. However,
subsequent words written to the FIFO do require a LOW on
RENfor access.
The state of the FWFT/SI input during Master Reset determines the timing
mode in use.
For applications requiring more data storage capacity than a single FIFO
can provide, the FWFT timing mode permits depth expansion by chaining
FIFOs in series (i.e. the data outputs of one FIFO are connected to the
corresponding data inputs of the next). No external logic is required.
These FIFOs have five flag pins,
EF/OR (Empty Flag or Output Ready),
FF/IR (Full Flag or Input Ready), HF (Half-full Flag), PAE (Programmable
Almost-Empty flag) and
PAF (Programmable Almost-Full flag). The EFand
FF functions are selected in IDT Standard mode. The IR and OR functions
are selected in FWFT mode.
HF, PAEand PAFare always available for use,
irrespective of timing mode.
PAE and PAF can be programmed independently to switch at any point
in memory. (See Table I and Table II.) Programmable offsets determine
the flag switching threshold and can be loaded by two methods: parallel or
serial. Two default offset settings are also provided, so that
PAE can be set
to switch at 127 or 1,023 locations from the empty boundary and the
PAF
threshold can be set at 127 or 1,023 locations from the full boundary. These
choices are made with the
LD pin during Master Reset.
DATA OUT (Q0 - Qn)
DATA IN (D0 - Dn)
MASTER RESET (MRS)
READ CLOCK (RCLK)
READ ENABLE (REN)
OUTPUT ENABLE (OE)
EMPTY FLAG/OUTPUT READY (EF/OR)
PROGRAMMABLE ALMOST-EMPTY (PAE)
WRITE CLOCK (WCLK)
WRITE ENABLE (WEN)
LOAD (LD)
FULL FLAG/INPUT READY (FF/IR)
PROGRAMMABLE ALMOST-FULL (PAF)
IDT
72V295
72V2105
PARTIAL RESET (PRS)
FIRST WORD FALL THROUGH/SERIAL INPUT
(FWFT/SI)
RETRANSMIT (RT)
4668 drw 03
HALF FULL FLAG (HF)
SERIAL ENABLE(SEN)
For serial programming,
SEN together with LD on each rising edge of
WCLK, are used to load the offset registers via the Serial Input (SI). For
parallel programming,
WEN together with LD on each rising edge of WCLK,
are used to load the offset registers via Dn.
REN together with LD on each
rising edge of RCLK can be used to read the offsets in parallel from Qn
regardless of whether serial or parallel offset loading has been selected.
During Master Reset (
MRS) the following events occur: The read and
write pointers are set to the first location of the FIFO. The FWFT pin selects
IDT Standard mode or FWFT mode. The
LD pin selects either a partial flag
default setting of 127 with parallel programming or a partial flag default
setting of 1,023 with serial programming. The flags are updated according
to the timing mode and default offsets selected.
The Partial Reset (
PRS) also sets the read and write pointers to the first
location of the memory. However, the timing mode, partial flag program-
ming method, and default or programmed offset settings existing before
Partial Reset remain unchanged. The flags are updated according to the
timing mode and offsets in effect.
PRSis useful for resetting a device in mid-
operation, when reprogramming partial flags would be undesirable.
The Retransmit function allows data to be reread from the FIFO. A LOW
on the
RT input during a rising RCLK edge initiates a retransmit operation
by setting the read pointer to the first location of the memory array.
If, at any time, the FIFO is not actively performing an operation, the chip
will automatically power down. Once in the power down state, the standby
supply current consumption is minimized. Initiating any operation (by
activating control inputs) will immediately take the device out of the power
down state.
The IDT72V295/72V2105 are fabricated using IDT’s high speed submi-
cron CMOS technology.
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| IDT72V2105L15PF | 功能描述:IC FIFO SUPERSYNCII 15NS 64-TQFP RoHS:否 类别:集成电路 (IC) >> 逻辑 - FIFO 系列:72V 标准包装:15 系列:74F 功能:异步 存储容量:256（64 x 4） 数据速率:- 访问时间:- 电源电压:4.5 V ~ 5.5 V 工作温度:0°C ~ 70°C 安装类型:通孔 封装/外壳:24-DIP（0.300"，7.62mm） 供应商设备封装:24-PDIP 包装:管件 其它名称:74F433 |
| IDT72V2105L15PF8 | 功能描述:IC FIFO SUPERSYNCII 15NS 64-TQFP RoHS:否 类别:集成电路 (IC) >> 逻辑 - FIFO 系列:72V 标准包装:15 系列:74F 功能:异步 存储容量:256（64 x 4） 数据速率:- 访问时间:- 电源电压:4.5 V ~ 5.5 V 工作温度:0°C ~ 70°C 安装类型:通孔 封装/外壳:24-DIP（0.300"，7.62mm） 供应商设备封装:24-PDIP 包装:管件 其它名称:74F433 |
| IDT72V2105L15PFGI | 功能描述:IC FIFO SUPERSYNCII 15NS 64-TQFP RoHS:是 类别:集成电路 (IC) >> 逻辑 - FIFO 系列:72V 标准包装:15 系列:74F 功能:异步 存储容量:256（64 x 4） 数据速率:- 访问时间:- 电源电压:4.5 V ~ 5.5 V 工作温度:0°C ~ 70°C 安装类型:通孔 封装/外壳:24-DIP（0.300"，7.62mm） 供应商设备封装:24-PDIP 包装:管件 其它名称:74F433 |
| IDT72V2105L15PFGI8 | 功能描述:IC FIFO SUPERSYNCII 15NS 64-TQFP RoHS:是 类别:集成电路 (IC) >> 逻辑 - FIFO 系列:72V 标准包装:15 系列:74F 功能:异步 存储容量:256（64 x 4） 数据速率:- 访问时间:- 电源电压:4.5 V ~ 5.5 V 工作温度:0°C ~ 70°C 安装类型:通孔 封装/外壳:24-DIP（0.300"，7.62mm） 供应商设备封装:24-PDIP 包装:管件 其它名称:74F433 |
| IDT72V2105L15PFI | 功能描述:IC FIFO SUPERSYNCII 15NS 64-TQFP RoHS:否 类别:集成电路 (IC) >> 逻辑 - FIFO 系列:72V 标准包装:15 系列:74F 功能:异步 存储容量:256（64 x 4） 数据速率:- 访问时间:- 电源电压:4.5 V ~ 5.5 V 工作温度:0°C ~ 70°C 安装类型:通孔 封装/外壳:24-DIP（0.300"，7.62mm） 供应商设备封装:24-PDIP 包装:管件 其它名称:74F433 |
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