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| 型号： | IDT72V2113L15PF |
| 厂商： | IDT, Integrated Device Technology Inc |
| 文件页数： | 14/46页 |
| 文件大小： | 0K |
| 描述： | IC FIFO SUPERSYNCII 15NS 80-TQFP |
| 标准包装： | 45 |
| 系列： | 72V |
| 功能： | 同步 |
| 存储容量： | 4.7Mb（262k x 18） |
| 访问时间： | 15ns |
| 电源电压： | 3.15 V ~ 3.45 V |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 80-LQFP |
| 供应商设备封装： | 80-TQFP（14x14） |
| 包装： | 托盘 |
| 其它名称： | 72V2113L15PF |
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IDT72V263/273/283/293/103/113 3.3V HIGH DENSITY SUPERSYNC IITM NARROW BUS FIFO
8K x 18, 16K x 9/18, 32K x 9/18, 64K x 9/18, 128K x 9/18, 256K x 9/18, 512K x9
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72V2103/72V2113 3.3V HIGH DENSITY SUPERSYNC IITM NARROW BUS FIFO
131,072 x 18/262,144 x 9, 262,144 x 18/524,288 x 9
JUNE 1, 2010
BUS-MATCHING (IW, OW)
The pins IW and OW are used to define the input and output bus widths.
DuringMasterReset,thestateofthesepinsisusedtoconfigurethedevicebus
sizes. See Table 1 for control settings. All flags will operate based on the word/
byte size boundary as defined by the selection of the widest input or output bus
width.
BIG-ENDIAN/LITTLE-ENDIAN (
BE)
During Master Reset, a LOW on
BE will select Big-Endian operation. A
HIGH on
BEduringMasterResetwillselectLittle-Endianformat.Thisfunction
is useful when data is written into the FIFO in word format (x18) and read out
of the FIFO in word format (x18) or byte format (x9). If Big-Endian mode is
selected, then the most significant byte of the word written into the FIFO will be
read out of the FIFO first, followed by the least significant byte. If Little-Endian
formatisselected,thentheleastsignificantbyteofthewordwrittenintotheFIFO
will be read out first, followed by the most significant byte. The mode desired
is configured during master reset by the state of the Big-Endian (
BE)pin.Refer
to Figure 4, Bus-Matching Byte Arrangement, for a diagram showing the byte
arrangement.
PROGRAMMABLE FLAG MODE (PFM)
During Master Reset During Master Reset, a LOW on PFM will select
Asynchronous Programmable flag timing mode. A HIGH on PFM will select
Synchronous Programmable flag timing mode. If asynchronous
PAF/PAE
configuration is selected (PFM, LOW during
MRS),thePAEisassertedLOW
on the LOW-to-HIGH transition of RCLK.
PAEisresettoHIGHontheLOW-to-
HIGH transition of WCLK. Similarly, the
PAFisassertedLOWontheLOW-to-
HIGH transition of WCLK and
PAF is reset to HIGH on the LOW-to-HIGH
transition of RCLK.
If synchronous
PAE/PAF configuration is selected (PFM, HIGH during
MRS) , the
PAE is asserted and updated on the rising edge of RCLK only and
not WCLK. Similarly,
PAFisassertedandupdatedontherisingedgeofWCLK
only and not RCLK. The mode desired is configured during master reset by the
state of the Programmable Flag Mode (PFM) pin.
INTERSPERSED PARITY (IP)
DuringMasterReset,aLOWonIPwillselectNon-InterspersedParitymode.
AHIGHwillselectInterspersedParitymode.TheIPbitfunctionallowstheuser
to select the parity bit in the word loaded into the parallel port (D0-Dn) when
programming the flag offsets. If Interspersed Parity mode is selected, then the
FIFO will assume that the parity bit is located in bit position D8 and D17 during
the parallel programming of the flag offsets, and will therefore ignore D8 when
loading the offset register in parallel mode. This is also applied to the output
register when reading the value of the offset register. If Interspersed Parity is
selected then output Q8 will be invalid. If Non-Interspersed Parity mode is
selected, then D16 and D17 are the parity bits and are ignored during parallel
programmingoftheoffsets.(D8becomesavalidbit).Additionally,outputQ8will
become a valid bit when performing a read of the offset register. IP mode is
selectedduringMasterResetbythestateoftheIPinputpin. InterspersedParity
control only has an effect during parallel programming of the offset registers. It
does not effect the data written to and read from the FIFO.
OUTPUTS:
FULL FLAG (
FF/IR)
Thisisadualpurposepin.InIDTStandardmode,theFullFlag(
FF)function
is selected. When the FIFO is full,
FF will go LOW, inhibiting further write
operations. When
FF is HIGH, the FIFO is not full. If no reads are performed
after a reset (either
MRS or PRS), FF will go LOW after D writes to the FIFO.
Ifx18Inputorx18OutputbusWidthisselected,D=131,072fortheIDT72V2103
and 262,144 for the IDT72V2113. If both x9 Input and x9 Output bus Widths
areselected,D = 262,144fortheIDT72V2103and524,288fortheIDT72V2113.
See Figure 7, Write Cycle and Full Flag Timing (IDT Standard Mode), for the
relevanttiminginformation.
In FWFT mode, the Input Ready (
IR) function is selected. IR goes LOW
when memory space is available for writing in data. When there is no longer
anyfreespaceleft,
IRgoesHIGH,inhibitingfurtherwriteoperations.Ifnoreads
are performed after a reset (either
MRSorPRS),IRwillgoHIGHafterD writes
to the FIFO. If x18 Input or x18 Output bus Width is selected, D = 131,073 for
the IDT72V2103 and 262,145 for the IDT72V2113. If both x9 Input and x9
OutputbusWidthsareselected,D=262,145fortheIDT72V2103and524,289
fortheIDT72V2113.SeeFigure9,WriteTiming(FWFTMode),fortherelevant
timinginformation.
The
IRstatusnotonlymeasuresthecontentsoftheFIFOmemory,butalso
counts the presence of a word in the output register. Thus, in FWFT mode, the
total number of writes necessary to deassert
IRisonegreaterthanneededto
assert
FF in IDT Standard mode.
FF/IRissynchronousandupdatedontherisingedgeofWCLK. FF/IRare
double register-buffered outputs.
EMPTY FLAG (
EF/OR)
This is a dual purpose pin. In the IDT Standard mode, the Empty Flag (
EF)
function is selected. When the FIFO is empty,
EFwillgoLOW,inhibitingfurther
read operations. When
EFisHIGH,theFIFOisnotempty.SeeFigure8,Read
Cycle, Empty Flag and First Word Latency Timing (IDT Standard Mode), for
therelevanttiminginformation.
InFWFTmode,theOutputReady(
OR)functionisselected.ORgoesLOW
at the same time that the first word written to an empty FIFO appears valid on
theoutputs.
ORstaysLOWaftertheRCLKLOWtoHIGHtransitionthatshiftsthe
last word from the FIFO memory to the outputs.
ORgoesHIGHonlywithatrue
read(RCLKwith
REN=LOW).Thepreviousdatastaysattheoutputs,indicating
the last word was read. Further data reads are inhibited until
OR goes LOW
again. See Figure 10, Read Timing (FWFT Mode), for the relevant timing
information.
EF/OR is synchronous and updated on the rising edge of RCLK.
In IDT Standard mode,
EF is a double register-buffered output. In FWFT
mode,
OR isatripleregister-bufferedoutput.
PROGRAMMABLE ALMOST-FULL FLAG (
PAF)
The Programmable Almost-Full flag (
PAF) will go LOW when the FIFO
reaches the almost-full condition. In IDT Standard mode, if no reads are
performed after reset (
MRS), PAF will go LOW after (D-m) words are written
totheFIFO.Ifx18Inputorx18OutputbusWidthisselected,(D-m) = (131,072-m)
writes for the IDT72V2103 and (262,144-m) writes for the IDT72V2113. If both
x9 Input and x9 Output bus Widths are selected, (D-m) = (262,144-m) writes
for the IDT72V2103 and (524,288-m) writes for the IDT72V2113. The offset
“m” is the full offset value. The default setting for this value is stated in Table 2.
In FWFT mode, if x18 Input or x18 Output bus Width is selected, the
PAF
will go LOW after (131,073-m) writes for the IDT72V2103 and (262,145-m)
writes for the IDT72V2113. If both x9 Input and x9 Output bus Widths are
selected,the
PAFwillgoLOWafter(262,145-m)writesfortheIDT72V2103and
(524,289-m)writesfortheIDT72V2113.Theoffsetmisthefulloffsetvalue.The
default setting for this value is stated in Table 2.
See Figure 18, Synchronous Programmable Almost-Full Flag Timing (IDT
Standard and FWFT Mode), for the relevant timing information.
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| IDT72V2113L6BC | 功能描述:IC FIFO SUPERSYNCII 6NS 100-BGA RoHS:否 类别:集成电路 (IC) >> 逻辑 - FIFO 系列:72V 标准包装:15 系列:74F 功能:异步 存储容量:256（64 x 4） 数据速率:- 访问时间:- 电源电压:4.5 V ~ 5.5 V 工作温度:0°C ~ 70°C 安装类型:通孔 封装/外壳:24-DIP（0.300"，7.62mm） 供应商设备封装:24-PDIP 包装:管件 其它名称:74F433 |
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| IDT72V2113L6PF8 | 功能描述:IC FIFO SUPERSYNCII 6NS 80-TQFP RoHS:否 类别:集成电路 (IC) >> 逻辑 - FIFO 系列:72V 标准包装:15 系列:74F 功能:异步 存储容量:256（64 x 4） 数据速率:- 访问时间:- 电源电压:4.5 V ~ 5.5 V 工作温度:0°C ~ 70°C 安装类型:通孔 封装/外壳:24-DIP（0.300"，7.62mm） 供应商设备封装:24-PDIP 包装:管件 其它名称:74F433 |
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