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| 型号： | IDT72V2113L6PFG |
| 厂商： | IDT, Integrated Device Technology Inc |
| 文件页数： | 10/46页 |
| 文件大小： | 0K |
| 描述： | IC FIFO SUPERSYNCII 6NS 80TQFP |
| 标准包装： | 45 |
| 系列： | 72V |
| 功能： | 同步 |
| 存储容量： | 4.7Mb（262k x 18） |
| 访问时间： | 4ns |
| 电源电压： | 3.15 V ~ 3.45 V |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 80-LQFP |
| 供应商设备封装： | 80-TQFP（14x14） |
| 包装： | 托盘 |
| 其它名称： | 72V2113L6PFG IDT72V2113L6PFG-ND |
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18
IDT72V263/273/283/293/103/113 3.3V HIGH DENSITY SUPERSYNC IITM NARROW BUS FIFO
8K x 18, 16K x 9/18, 32K x 9/18, 64K x 9/18, 128K x 9/18, 256K x 9/18, 512K x9
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72V2103/72V2113 3.3V HIGH DENSITY SUPERSYNC IITM NARROW BUS FIFO
131,072 x 18/262,144 x 9, 262,144 x 18/524,288 x 9
JUNE 1, 2010
RETRANSMIT OPERATION
The Retransmit operation allows data that has already been read to be
accessed again. There are 2 modes of Retransmit operation, normal latency
and zero latency. There are two stages to Retransmit: first, a setup procedure
that resets the read pointer to the first location of memory, then the actual
retransmit, which consists of reading out the memory contents, starting at the
beginning of memory.
Retransmitsetupisinitiatedbyholding
RTLOWduringarisingRCLKedge.
RENandWEN mustbeHIGHbeforebringingRTLOW.Whenzerolatencyis
utilized,
REN doesnotneedtobeHIGHbeforebringingRTLOW. Atleasttwo
words, but no more than D - 2 words should have been written into the FIFO,
and read from the FIFO, between Reset (Master or Partial) and the time of
Retransmitsetup.Ifx18Inputorx18OutputbusWidthisselected,D=131,072
for the IDT72V2103 and 262,144 for the IDT72V2113. If both x9 Input and x9
OutputbusWidthsareselected,D=262,144fortheIDT72V2103and524,288
for the IDT72V2113. In FWFT mode, if x18 Input or x18 Output bus Width is
selected, D = 131,073 for the IDT72V2103 and 262,145 for the IDT72V2113.
If both x9 Input and x9 Output bus Widths are selected, D = 262,145 for the
IDT72V2103 and 524,289 for the IDT72V2113.
If IDT Standard mode is selected, the FIFO will mark the beginning of the
Retransmitsetupbysetting
EFLOW.Thechangeinlevelwillonlybenoticeable
if
EF was HIGH before setup. During this period, the internal read pointer is
initialized to the first location of the RAM array.
When
EF goes HIGH, Retransmit setup is complete and read operations
may begin starting with the first location in memory. Since IDT Standard mode
is selected, every word read including the first word following Retransmit setup
requires a LOW on
REN to enable the rising edge of RCLK. See Figure 11,
Retransmit Timing (IDT Standard Mode), for the relevant timing diagram.
IfFWFTmodeisselected,theFIFOwillmarkthebeginningoftheRetransmit
setup by setting
OR HIGH. During this period, the internal read pointer is set
to the first location of the RAM array.
When
ORgoesLOW,Retransmitsetupiscomplete;atthesametime,the
contentsofthefirstlocationappearontheoutputs.SinceFWFTmodeisselected,
the first word appears on the outputs, no LOW on
RENisnecessary.Reading
all subsequent words requires a LOW on
REN to enable the rising edge of
RCLK.SeeFigure12,RetransmitTiming(FWFTMode),fortherelevanttiming
diagram.
ForeitherIDTStandardmodeorFWFTmode,updatingofthe
PAE,HFand
PAF flags begin with the rising edge of RCLK that the RT is setup on. PAE is
synchronizedtoRCLK,thusonthesecondrisingedgeofRCLKafter
RTissetup,
the
PAEflagwillbeupdated.HFisasynchronous,thustherisingedgeofRCLK
that
RTissetupwillupdateHF.PAFissynchronizedtoWCLK,thusthesecond
rising edge of WCLK that occurs tSKEW after the rising edge of RCLK that
RT
is setup will update
PAF. RT is synchronized to RCLK.
TheRetransmitfunctionhastheoptionof2modesofoperation,either"normal
latency" or "zero latency". Figure 11 and Figure 12 mentioned previously,
relate to "normal latency". Figure 13 and Figure 14 show "zero latency"
retransmitoperation.Zerolatencybasicallymeansthatthefirstdatawordtobe
retransmitted,isplacedontotheoutputregisterwithrespecttotheRCLKpulse
thatinitiatedtheretransmit.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| IDT72V2113L7-5BC | 功能描述:IC FIFO SUPERSYNCII 7-5NS 100BGA RoHS:否 类别:集成电路 (IC) >> 逻辑 - FIFO 系列:72V 标准包装:90 系列:74ABT 功能:同步，双端口 存储容量:4.6K（64 x 36 x2） 数据速率:67MHz 访问时间:- 电源电压:4.5 V ~ 5.5 V 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:120-LQFP 裸露焊盘 供应商设备封装:120-HLQFP（14x14） 包装:托盘 产品目录页面:1005 (CN2011-ZH PDF) 其它名称:296-3984 |
| IDT72V2113L7-5BCGI | 制造商:Integrated Device Technology Inc 功能描述:IC FIFO SYNC 3.3V 5NS 100-LBGA |
| IDT72V2113L7-5BCGI8 | 制造商:Integrated Device Technology Inc 功能描述:IC FIFO SYNC 3.3V 5NS 100-LBGA |
| IDT72V2113L7-5BCI | 功能描述:IC FIFO SYNC 3.3V 5NS 100-LBGA RoHS:否 类别:集成电路 (IC) >> 逻辑 - FIFO 系列:72V 标准包装:90 系列:74ABT 功能:同步，双端口 存储容量:4.6K（64 x 36 x2） 数据速率:67MHz 访问时间:- 电源电压:4.5 V ~ 5.5 V 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:120-LQFP 裸露焊盘 供应商设备封装:120-HLQFP（14x14） 包装:托盘 产品目录页面:1005 (CN2011-ZH PDF) 其它名称:296-3984 |
| IDT72V2113L7-5PF | 功能描述:IC FIFO SUPERSYNCII 7-5NS 80TQFP RoHS:否 类别:集成电路 (IC) >> 逻辑 - FIFO 系列:72V 标准包装:15 系列:74F 功能:异步 存储容量:256（64 x 4） 数据速率:- 访问时间:- 电源电压:4.5 V ~ 5.5 V 工作温度:0°C ~ 70°C 安装类型:通孔 封装/外壳:24-DIP（0.300"，7.62mm） 供应商设备封装:24-PDIP 包装:管件 其它名称:74F433 |
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