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参数资料
| 型号： | IDT72V221L15PFG |
| 厂商： | IDT, Integrated Device Technology Inc |
| 文件页数： | 3/14页 |
| 文件大小： | 0K |
| 描述： | IC FIFO SYNC 1KX9 15NS 32QFP |
| 标准包装： | 1 |
| 系列： | 72V |
| 功能： | 同步 |
| 存储容量： | 9K（1K x 9） |
| 访问时间： | 15ns |
| 电源电压： | 3 V ~ 3.6 V |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 32-LQFP |
| 供应商设备封装： | 32-TQFP（7x7） |
| 包装： | 托盘 |
| 产品目录页面： | 1255 (CN2011-ZH PDF) |
| 其它名称： | 72V221L15PFG 800-1516 |
11
IDT72V201/72V211/72V221/72V231/72V241/72V251 3.3V CMOS SyncFIFO
256 x 9, 512 x 9, 1,024 x 9, 2,048 x 9, 4,096 x 9 and 8,192 x 9
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
NOTES:
1. m = PAF offset.
2. 256 - m words in FIFO for IDT72V201, 512 - m words for IDT72V211, 1,024 - m words for IDT72V221, 2,048 - m words for IDT72V231, 4,096 - m words for IDT72V241, 8,192 - m
words for IDT72V251.
3. tSKEW2 is the minimum time between a rising RCLK edge and a rising WCLK edge for PAF to change during that clock cycle. If the time between the rising edge of RCLK and
the rising edge of WCLK is less than tSKEW2, then PAF may not change state until the next WCLK rising edge.
4. If a write is performed on this rising edge of the write clock, there will be Full - (m-1) words in the FIFO when PAF goes LOW.
NOTES:
1. n = PAE offset.
2. tSKEW2 is the minimum time between a rising WCLK edge and a rising RCLK edge for PAE to change during that clock cycle. If the time between the rising edge of WCLK and
the rising edge of RCLK is less than tSKEW2, then PAE may not change state until the next RCLK rising edge.
3. If a read is performed on this rising edge of the read clock, there will be Empty + (n-1) words in the FIFO when PAE goes LOW.
Figure 11. Programmable Empty Flag Timing
Figure 10. Programmable Full Flag Timing
tENS
tENH
tENS
tENH
tENS
tENH
WCLK
WEN1
WEN2
(If Applicable)
PAF
RCLK
REN1,
REN2
(4)
(1)
tPAF
Full - (m + 1) words in FIFO
Full - m words in FIFO
(2)
tCLKH
tCLKL
tSKEW2
(3)
tPAF
4092 drw12
WCLK
WEN1
WEN2
PAE
RCLK
REN1,
REN2
tENS
tENH
tENS
tENH
tSKEW2
(2)
tENS
tENH
(If Applicable)
tPAE
(3)
(1)
n words in FIFO
n + 1 words in FIFO
tCLKH
tCLKL
4092 drw13
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相关代理商/技术参数 |
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| IDT72V221L15PFG8 | 制造商:Integrated Device Technology Inc 功能描述:IC FIFO SYNC 1KX9 15NS 32QFP |
| IDT72V221L15PFGI | 制造商:Integrated Device Technology Inc 功能描述:IC FIFO SYNC 1KX9 15NS 32QFP |
| IDT72V221L15PFGI8 | 制造商:Integrated Device Technology Inc 功能描述:IC FIFO SYNC 1KX9 15NS 32QFP |
| IDT72V221L15PFI | 功能描述:IC FIFO SYNC 1KX9 15NS 32QFP RoHS:否 类别:集成电路 (IC) >> 逻辑 - FIFO 系列:72V 标准包装:80 系列:7200 功能:同步 存储容量:18.4K（1K x 18） 数据速率:- 访问时间:10ns 电源电压:4.5 V ~ 5.5 V 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:64-LQFP 供应商设备封装:64-TQFP（10x10） 包装:托盘 其它名称:72225LB10TF |
| IDT72V221L15PFI8 | 功能描述:IC FIFO SYNC 1KX9 15NS 32QFP RoHS:否 类别:集成电路 (IC) >> 逻辑 - FIFO 系列:72V 标准包装:80 系列:7200 功能:同步 存储容量:18.4K（1K x 18） 数据速率:- 访问时间:10ns 电源电压:4.5 V ~ 5.5 V 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:64-LQFP 供应商设备封装:64-TQFP（10x10） 包装:托盘 其它名称:72225LB10TF |
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