参数资料
型号: IDT72V251L15PFI
厂商: INTEGRATED DEVICE TECHNOLOGY INC
元件分类: FIFO
英文描述: Hex inverting Schmitt trigger - Description: Hex Inverter Schmitt Trigger ; Logic switching levels: CMOS ; Number of pins: 14 ; Output drive capability: +/- 8 mA ; Power dissipation considerations: Low Power or Battery Applications ; Propagation delay: 3.2@5V ns; Voltage: 2.0-5.5 V
中文描述: 8K X 9 OTHER FIFO, 10 ns, PQFP32
封装: PLASTIC, TQFP-32
文件页数: 1/14页
文件大小: 156K
代理商: IDT72V251L15PFI
1
3.3 VOLT CMOS SyncFIFO
256 x 9, 512 x 9,
1,024 x 9, 2,048 x 9,
4,096 x 9 and 8,192 x 9
IDT72V201, IDT72V211
IDT72V221, IDT72V231
IDT72V241, IDT72V251
2002 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.
DSC-4092/3
FEBRUARY 2002
IDT and the IDT logo are trademarks of Integrated Device Technology, Inc. SyncFIFO is a trademark of Integrated Device Technology, Inc.
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
clocked read and write controls. The architecture, functional operation and pin
assignments are identical to those of the IDT72201/72211/72221/72231/
72241/72251, but operate at a power supply voltage (Vcc) between 3.0V and
3.6V. These devices have a 256, 512, 1,024, 2,048, 4,096 and 8,192 x 9-bit
memory array, respectively. These FIFOs are applicable for a wide variety of
databufferingneedssuchasgraphics,localareanetworksandinterprocessor
communication.
These FIFOs have 9-bit input and output ports. The input port is
controlled by a free-running clock (WCLK), and two Write Enable pins
(
WEN1, WEN2). Data is written into the Synchronous FIFO on every rising
clock edge when the Write Enable pins are asserted. The output port is
controlled by another clock pin (RCLK) and two Read Enable pins (
REN1,
REN2). The Read Clock can be tied to the Write Clock for single clock
operation or the two clocks can run asynchronous of one another for dual-
clock operation. An Output Enable pin (
OE) is provided on the read port
for three-state control of the output.
The Synchronous FIFOs have two fixed flags, Empty (
EF) and Full (FF).
Two programmable flags, Almost-Empty (
PAE) and Almost-Full (PAF), are
provided for improved system control. The programmable flags default to
Empty+7 and Full-7 for
PAE and PAF, respectively. The programmable flag
offsetloadingiscontrolledbyasimplestatemachineandisinitiatedbyasserting
the Load pin (
LD).
These FIFOs are fabricated using IDT's high-speed submicron CMOS
technology.
FEATURES:
256 x 9-bit organization IDT72V201
512 x 9-bit organization IDT72V211
1,024 x 9-bit organization IDT72V221
2,048 x 9-bit organization IDT72V231
4,096 x 9-bit organization IDT72V241
8,192 x 9-bit organization IDT72V251
10 ns read/write cycle time
5V input tolerant
Read and Write clocks can be independent
Dual-Ported zero fall-through time architecture
Empty and Full Flags signal FIFO status
Programmable Almost-Empty and Almost-Full flags can be set to
any depth
Programmable Almost-Empty and Almost-Full flags default to
Empty+7, and Full-7, respectively
Output Enable puts output data bus in high-impedance state
Advanced submicron CMOS technology
Available in 32-pin plastic leaded chip carrier (PLCC) and 32-pin
plastic Thin Quad FlatPack (TQFP)
Industrial temperature range (–40
°°°°°C to +85°°°°°C) is available
DESCRIPTION:
TheIDT72V201/72V211/72V221/72V231/72V241/72V251SyncFIFOs
are very high-speed, low-power First-In, First-Out (FIFO) memories with
FUNCTIONAL BLOCK DIAGRAM
WCLK
WEN1
WEN2
D0 - D8
LD
OFFSET REGISTER
INPUT REGISTER
RAM ARRAY
256 x 9, 512 x 9,
1,024 x 9, 2,048 x 9,
4,096 x 9, 8,192 x 9
WRITE CONTROL
LOGIC
WRITE POINTER
RESET LOGIC
OUTPUT REGISTER
OE
RS
Q0 - Q8
RCLK
REN1
REN2
READ CONTROL
LOGIC
READ POINTER
FLAG
LOGIC
EF
PAE
PAF
FF
4092 drw 01
相关PDF资料
PDF描述
IDT72V251L20J Quad 2-input multiplexer - Description: Quad 2-Input Multiplexer ; Logic switching levels: CMOS ; Number of pins: 16 ; Output drive capability: +/- 8 mA ; Power dissipation considerations: Low Power or Battery Applications ; Propagation delay: 3.2@5V ns; Voltage: 2.0-5.5 V
IDT72V251L20PF 8-bit serial-in/parallel-out shift register - Description: 8-Bit Serial-In/Parallel-Out Shift Register ; F<sub>max</sub>: 115 MHz; Logic switching levels: CMOS ; Output drive capability: +/- 8 mA ; Power dissipation considerations: Low Power or Battery Applications ; Propagation delay: 4.5@5V ns; Voltage: 2.0-5.5 V
IDT72V255LA15PF 2-input NOR gate - Description: Picogate 2 input NOR Gate ; Logic switching levels: CMOS ; Number of pins: 5 ; Output drive capability: +/- 8 mA ; Power dissipation considerations: Low Power or Battery Applications ; Propagation delay: 3.2@5V ns; Voltage: 2.0-5.5 V
IDT72V255LA15PFI 3.3 VOLT CMOS SuperSync FIFO 8,192 x 18 16,384 x 18
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相关代理商/技术参数
参数描述
IDT72V251L15PFI8 功能描述:IC FIFO SYNC 4096X18 15NS 32QFP RoHS:否 类别:集成电路 (IC) >> 逻辑 - FIFO 系列:72V 标准包装:80 系列:7200 功能:同步 存储容量:18.4K(1K x 18) 数据速率:- 访问时间:10ns 电源电压:4.5 V ~ 5.5 V 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:64-LQFP 供应商设备封装:64-TQFP(10x10) 包装:托盘 其它名称:72225LB10TF
IDT72V251L20J 功能描述:IC FIFO SYNC 4096X18 20NS 32PLCC RoHS:否 类别:集成电路 (IC) >> 逻辑 - FIFO 系列:72V 标准包装:80 系列:7200 功能:同步 存储容量:18.4K(1K x 18) 数据速率:- 访问时间:10ns 电源电压:4.5 V ~ 5.5 V 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:64-LQFP 供应商设备封装:64-TQFP(10x10) 包装:托盘 其它名称:72225LB10TF
IDT72V251L20J8 功能描述:IC FIFO SYNC 4096X18 20NS 32PLCC RoHS:否 类别:集成电路 (IC) >> 逻辑 - FIFO 系列:72V 标准包装:80 系列:7200 功能:同步 存储容量:18.4K(1K x 18) 数据速率:- 访问时间:10ns 电源电压:4.5 V ~ 5.5 V 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:64-LQFP 供应商设备封装:64-TQFP(10x10) 包装:托盘 其它名称:72225LB10TF
IDT72V251L20PF 功能描述:IC FIFO SYNC 4096X18 20NS 32QFP RoHS:否 类别:集成电路 (IC) >> 逻辑 - FIFO 系列:72V 标准包装:80 系列:7200 功能:同步 存储容量:18.4K(1K x 18) 数据速率:- 访问时间:10ns 电源电压:4.5 V ~ 5.5 V 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:64-LQFP 供应商设备封装:64-TQFP(10x10) 包装:托盘 其它名称:72225LB10TF
IDT72V251L20PF8 功能描述:IC FIFO SYNC 4096X18 20NS 32QFP RoHS:否 类别:集成电路 (IC) >> 逻辑 - FIFO 系列:72V 标准包装:80 系列:7200 功能:同步 存储容量:18.4K(1K x 18) 数据速率:- 访问时间:10ns 电源电压:4.5 V ~ 5.5 V 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:64-LQFP 供应商设备封装:64-TQFP(10x10) 包装:托盘 其它名称:72225LB10TF