参数资料
型号: IDT72V255LA20TF
厂商: IDT, Integrated Device Technology Inc
文件页数: 3/27页
文件大小: 0K
描述: IC FIFO SS 8192X18 20NS 64-STQFP
标准包装: 80
系列: 72V
功能: 同步
存储容量: 144K(8K x 18)
访问时间: 20ns
电源电压: 3 V ~ 3.6 V
工作温度: 0°C ~ 70°C
安装类型: 表面贴装
封装/外壳: 64-LQFP
供应商设备封装: 64-TQFP(10x10)
包装: 托盘
其它名称: 72V255LA20TF
11
IDT72V255LA/72V265LA 3.3 VOLT CMOS SuperSync FIFO
8,192 x 18, 16,384 x 18
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
OCTOBER 22, 2008
If FWFT mode is selected, the FIFO will mark the beginning of the
Retransmit setup by setting
OR HIGH. During this period, the internal read
pointer is set to the first location of the RAM array.
When
OR goes LOW, Retransmit setup is complete; at the same time, the
contents of the first location appear on the outputs. Since FWFT mode is
selected, the first word appears on the outputs, no LOW on
REN is
necessary. Reading all subsequent words requires a LOW on
REN to
enable the rising edge of RCLK. See Figure 12, Retransmit Timing (FWFT
Mode), for the relevant timing diagram.
For either IDT Standard mode or FWFT mode, updating of the
PAE, HF
and
PAF flags begin with the rising edge of RCLK that RT is setup. PAE is
synchronized to RCLK, thus on the second rising edge of RCLK after
RT is
setup, the
PAE flag will be updated. HF is asynchronous, thus the rising
edge of RCLK that
RT is setup will update HF. PAF is synchronized to
WCLK, thus the second rising edge of WCLK that occurs tSKEW after the
rising edge of RCLK that
RT is setup will update PAF. RT is synchronized to
RCLK.
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IDT72V261LA10PF8 功能描述:IC FIFO SS 8192X18 10NS 64QFP RoHS:否 类别:集成电路 (IC) >> 逻辑 - FIFO 系列:72V 标准包装:90 系列:7200 功能:同步 存储容量:288K(16K x 18) 数据速率:100MHz 访问时间:10ns 电源电压:4.5 V ~ 5.5 V 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:64-LQFP 供应商设备封装:64-TQFP(14x14) 包装:托盘 其它名称:72271LA10PF
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IDT72V261LA10PFG8 制造商:Integrated Device Technology Inc 功能描述:IC FIFO SS 8192X18 10NS 64TQFP