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参数资料
| 型号： | IDT72V265LA15TF |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | FIFO |
| 英文描述： | 3.3 VOLT CMOS SuperSync FIFO 8,192 x 18 16,384 x 18 |
| 中文描述： | 16K X 18 OTHER FIFO, 10 ns, PQFP64 |
| 封装： | SLIM, TQFP-64 |
| 文件页数： | 26/27页 |
| 文件大小： | 439K |
| 代理商： | IDT72V265LA15TF |
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8
IDT72V255LA/72V265LA 3.3 VOLT CMOS SuperSync FIFO
8,192 x 18, 16,384 x 18
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
PROGRAMMING FLAG OFFSETS
Full and Empty Flag offset values are user programmable. The
IDT72V255LA/72V265LA has internal registers for these offsets. Default
settings are stated in the footnotes of Table 1 and Table 2. Offset values can
be programmed into the FIFO in one of two ways; serial or parallel loading
method. The selection of the loading method is done using the
LD (Load)
pin. During Master Reset, the state of the
LD input determines whether
serial or parallel flag offset programming is enabled. A HIGH on
LD during
Master Reset selects serial loading of offset values and in addition, sets a
default
PAE offset value of 3FFH (a threshold 1,023 words from the empty
boundary), and a default
PAF offset value of 3FFH (a threshold 1,023
words from the full boundary). A LOW on
LD during Master Reset selects
parallel loading of offset values, and in addition, sets a default
PAE offset
72V255LA
72V265LA
FF PAF HF PAE EF
00
H
L
1 to n (1)
HH
H
L
H
(n + 1) to 4,096
(n + 1) to 8,192
H
4,097 to (8,192–(m+1))
8,193 to (16,384–(m+1))
H
HLH
H
(8,192–m)(2) to 8,191
(16,384–m) (2) to 16,383
H
L
H
8,192
16,384
L
H
NOTES:
1. n = Empty Offset, Default Values: n = 127 when parallel offset loading is selected or n = 1,023 when serial offset loading is selected.
2. m = Full Offset, Default Values: m = 127 when parallel offset loading is selected or m = 1,023 when serial offset loading is selected.
TABLE 1 STATUS FLAGS FOR IDT STANDARD MODE
Number of
Words in
FIFO
72V255LA
72V265LA
FF PAF HF PAE EF
00
L
H
L
H
1 to n+1 (1)
LH
H
L
(n + 2) to 4,097
(n + 2) to 8,193
L
H
L
4,098 to (8,193–(m+1))(2)
8,194 to (16,385–(m+1)) (2)
LH
L
H
L
(8,193–m) to 8,192
(16,385–m) (2) to 16,384
L
H
L
8,193
16,385
H
L
H
L
NOTES:
1. n = Empty Offset, Default Values: n = 127 when parallel offset loading is selected or n = 1,023 when serial offset loading is selected.
2. m = Full Offset, Default Values: m = 127 when parallel offset loading is selected or m = 1,023 when serial offset loading is selected.
TABLE 2 STATUS FLAGS FOR FWFT MODE
Number of
Words in
FIFO (1)
4672 drw 05
value of 07FH (a threshold 127 words from the empty boundary), and a
default
PAF offset value of 07FH (a threshold 127 words from the full
boundary). See Figure 3, Offset Register Location and Default Values.
In addition to loading offset values into the FIFO, it also possible to read
the current offset values. It is only possible to read offset values via parallel
read.
Figure 4, Programmable Flag Offset Programming Sequence, summa-
rizes the control pins and sequence for both serial and parallel program-
ming modes. For a more detailed description, see discussion that follows.
The offset registers may be programmed (and reprogrammed) any time
after Master Reset, regardless of whether serial or parallel programming
has been selected.
相关PDF资料 |
PDF描述 |
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| IDT72V265LA15TFI | 3.3 VOLT CMOS SuperSync FIFO 8,192 x 18 16,384 x 18 |
| IDT72V265LA20PF | Dual 2-input AND gate - Description: Dual 2-Input AND Gate ; Logic switching levels: CMOS ; Number of pins: 8 ; Output drive capability: +/- 8 mA ; Power dissipation considerations: Low Power or Battery Applications ; Propagation delay: 3.2@5V ns; Voltage: 2.0-5.5 V |
| IDT72V265LA20TF | 3.3 VOLT CMOS SuperSync FIFO 8,192 x 18 16,384 x 18 |
| IDT72V255LA | 2-input NAND gate - Description: PicoGate 2-Input NAND Gate ; Logic switching levels: CMOS ; Number of pins: 5 ; Output drive capability: +/- 8 mA ; Power dissipation considerations: Low Power or Battery Applications ; Propagation delay: 3.5@5V ns; Voltage: 2.0-5.5 V |
| IDT72V255LA10TFI | 2-input NOR gate - Description: Picogate 2 input NOR Gate ; Logic switching levels: CMOS ; Number of pins: 5 ; Output drive capability: +/- 8 mA ; Power dissipation considerations: Low Power or Battery Applications ; Propagation delay: 3.2@5V ns; Voltage: 2.0-5.5 V |
相关代理商/技术参数 |
参数描述 |
|---|---|
| IDT72V265LA15TF8 | 功能描述:IC FIFO SS 16384X18 15NS 64STQFP RoHS:否 类别:集成电路 (IC) >> 逻辑 - FIFO 系列:72V 标准包装:90 系列:7200 功能:同步 存储容量:288K（16K x 18） 数据速率:100MHz 访问时间:10ns 电源电压:4.5 V ~ 5.5 V 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:64-LQFP 供应商设备封装:64-TQFP（14x14） 包装:托盘 其它名称:72271LA10PF |
| IDT72V265LA15TFGI | 功能描述:IC FIFO SS 16384X18 15NS 64STQFP RoHS:是 类别:集成电路 (IC) >> 逻辑 - FIFO 系列:72V 标准包装:90 系列:7200 功能:同步 存储容量:288K（16K x 18） 数据速率:100MHz 访问时间:10ns 电源电压:4.5 V ~ 5.5 V 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:64-LQFP 供应商设备封装:64-TQFP（14x14） 包装:托盘 其它名称:72271LA10PF |
| IDT72V265LA15TFGI8 | 功能描述:IC FIFO SS 16384X18 15NS 64STQFP RoHS:是 类别:集成电路 (IC) >> 逻辑 - FIFO 系列:72V 标准包装:90 系列:7200 功能:同步 存储容量:288K（16K x 18） 数据速率:100MHz 访问时间:10ns 电源电压:4.5 V ~ 5.5 V 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:64-LQFP 供应商设备封装:64-TQFP（14x14） 包装:托盘 其它名称:72271LA10PF |
| IDT72V265LA15TFI | 功能描述:IC FIFO SS 16384X18 15NS 64STQFP RoHS:否 类别:集成电路 (IC) >> 逻辑 - FIFO 系列:72V 标准包装:90 系列:74ABT 功能:同步，双端口 存储容量:4.6K（64 x 36 x2） 数据速率:67MHz 访问时间:- 电源电压:4.5 V ~ 5.5 V 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:120-LQFP 裸露焊盘 供应商设备封装:120-HLQFP（14x14） 包装:托盘 产品目录页面:1005 (CN2011-ZH PDF) 其它名称:296-3984 |
| IDT72V265LA15TFI8 | 功能描述:IC FIFO SS 16384X18 15NS 64STQFP RoHS:否 类别:集成电路 (IC) >> 逻辑 - FIFO 系列:72V 标准包装:90 系列:7200 功能:同步 存储容量:288K（16K x 18） 数据速率:100MHz 访问时间:10ns 电源电压:4.5 V ~ 5.5 V 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:64-LQFP 供应商设备封装:64-TQFP（14x14） 包装:托盘 其它名称:72271LA10PF |
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