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参数资料
| 型号： | IDT72V275L15TF8 |
| 厂商： | IDT, Integrated Device Technology Inc |
| 文件页数： | 5/25页 |
| 文件大小： | 0K |
| 描述： | IC FIFO SS 32768X18 15NS 64STQFP |
| 标准包装： | 1,250 |
| 系列： | 72V |
| 功能： | 同步 |
| 存储容量： | 589K（32K x 18） |
| 访问时间： | 15ns |
| 电源电压： | 3 V ~ 3.6 V |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 64-LQFP |
| 供应商设备封装： | 64-TQFP（10x10） |
| 包装： | 带卷 (TR) |
| 其它名称： | 72V275L15TF8 |
13
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72V275/72V285 3.3V CMOS SUPERSYNC FIFOTM
32,768 x 18 and 65,536 x 18
PROGRAMMABLE ALMOST-FULL FLAG (
PAF
PAF)
The Programmable Almost-Full flag (
PAF) will go LOW when the FIFO
reaches the almost-full condition. In IDT Standard mode, if no reads are
performedafterreset(
MRS),PAFwillgoLOWafter(D - m)wordsarewritten
to the FIFO. The
PAFwillgoLOWafter(32,768-m)writesfortheIDT72V275
and (65,536-m)writesfortheIDT72V285.Theoffset“m”isthefulloffsetvalue.
The default setting for this value is stated in the footnote of Table 1.
In FWFT mode, the
PAF will go LOW after (32,769-m) writes for the
IDT72V275and(65,537-m)writesfortheIDT72V285,wheremisthefulloffset
value. The default setting for this value is stated in the footnote of Table 2.
See Figure 16, Programmable Almost-Full Flag Timing (IDT Standard
and FWFT Mode), for the relevant timing information.
PAF is synchronous and updated on the rising edge of WCLK.
PROGRAMMABLE ALMOST-EMPTY FLAG (
PAE
PAE)
TheProgrammableAlmost-Emptyflag(
PAE)willgoLOWwhentheFIFO
reachesthealmost-emptycondition.InIDTStandardmode,
PAEwillgoLOW
when there are n words or less in the FIFO. The offset “n” is the empty offset
value. The default setting for this value is stated in the footnote of Table 1.
In FWFT mode, the
PAE will go LOW when there are n+1 words or less
intheFIFO.ThedefaultsettingforthisvalueisstatedinthefootnoteofTable2.
See Figure 17, Programmable Almost-Empty Flag Timing (IDT Standard
and FWFT Mode), for the relevant timing information.
PAE is synchronous and updated on the rising edge of RCLK.
HALF-FULL FLAG (
HF
HF)
Thisoutputindicatesahalf-fullFIFO.TherisingWCLKedgethatfillstheFIFO
beyond half-full sets
HF LOW. The flag remains LOW until the difference
between the write and read pointers becomes less than or equal to half of the
totaldepthofthedevice;therisingRCLKedgethataccomplishesthiscondition
sets
HF HIGH.
In IDT Standard mode, if no reads are performed after reset (
MRS or
PRS), HF will go LOW after (D/2 + 1) writes to the FIFO, where D = 32,768
for the IDT72V275 and 65,536 for the IDT72V285.
In FWFT mode, if no reads are performed after reset (
MRSorPRS),HF
will go LOW after (D-1/2 + 2) writes to the FIFO, where D = 32,769 for the
IDT72V275 and 65,537 for the IDT72V285.
See Figure 18, Half-Full Flag Timing (IDT Standard and FWFT Modes),
for the relevant timing information. Because
HFisupdatedbybothRCLKand
WCLK, it is considered asynchronous.
DATA OUTPUTS (Q0-Q17)
(Q0 - Q17) are data outputs for 18-bit wide data.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| IDT72V275L15TFGI | 制造商:Integrated Device Technology Inc 功能描述:IC FIFO SS 32768X18 15NS 64STQFP |
| IDT72V275L15TFGI8 | 制造商:Integrated Device Technology Inc 功能描述:IC FIFO SS 32768X18 15NS 64STQFP |
| IDT72V275L15TFI | 功能描述:IC FIFO SS 32768X18 15NS 64STQFP RoHS:否 类别:集成电路 (IC) >> 逻辑 - FIFO 系列:72V 标准包装:15 系列:74F 功能:异步 存储容量:256（64 x 4） 数据速率:- 访问时间:- 电源电压:4.5 V ~ 5.5 V 工作温度:0°C ~ 70°C 安装类型:通孔 封装/外壳:24-DIP（0.300"，7.62mm） 供应商设备封装:24-PDIP 包装:管件 其它名称:74F433 |
| IDT72V275L15TFI8 | 功能描述:IC FIFO SS 32768X18 15NS 64STQFP RoHS:否 类别:集成电路 (IC) >> 逻辑 - FIFO 系列:72V 标准包装:15 系列:74F 功能:异步 存储容量:256（64 x 4） 数据速率:- 访问时间:- 电源电压:4.5 V ~ 5.5 V 工作温度:0°C ~ 70°C 安装类型:通孔 封装/外壳:24-DIP（0.300"，7.62mm） 供应商设备封装:24-PDIP 包装:管件 其它名称:74F433 |
| IDT72V275L20PF | 功能描述:IC FIFO SS 32768X18 20NS 64-TQFP RoHS:否 类别:集成电路 (IC) >> 逻辑 - FIFO 系列:72V 标准包装:15 系列:74F 功能:异步 存储容量:256（64 x 4） 数据速率:- 访问时间:- 电源电压:4.5 V ~ 5.5 V 工作温度:0°C ~ 70°C 安装类型:通孔 封装/外壳:24-DIP（0.300"，7.62mm） 供应商设备封装:24-PDIP 包装:管件 其它名称:74F433 |
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