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参数资料
| 型号： | IDT72V3611L15PF8 |
| 厂商： | IDT, Integrated Device Technology Inc |
| 文件页数： | 1/19页 |
| 文件大小： | 0K |
| 描述： | IC FIFO SYNC 64X36 15NS 120-TQFP |
| 标准包装： | 750 |
| 系列： | 72V |
| 功能： | 同步 |
| 存储容量： | 2.3K（64 x 36） |
| 数据速率： | 67MHz |
| 访问时间： | 15ns |
| 电源电压： | 3 V ~ 3.6 V |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 120-LQFP |
| 供应商设备封装： | 120-TQFP（14x14） |
| 包装： | 带卷 (TR) |
| 其它名称： | 72V3611L15PF8 |
1
3.3 VOLT CMOS SyncFIFOTM
64 x 36
IDT72V3611
2014 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.
DSC-4657/5
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. SyncFIFO is a trademark of Integrated Device Technology, Inc.
COMMERCIAL TEMPERATURE RANGE
JANUARY 2014
FEATURES:
64 x 36 storage capacity
Supports clock frequencies up to 67MHz
Fast access times of 10ns
Free-running CLKA and CLKB may be asynchronous or
coincident (permits simultaneous reading and writing of
data on a single clock edge)
Synchronous data buffering from Port A to Port B
Mailbox bypass register in each direction
Programmable Almost-Full (AF) and Almost-Empty (AE) flags
Microprocessor Interface Control Logic
Full Flag (FF) and Almost-Full (AF) flags synchronized by CLKA
Empty Flag (EF) and Almost-Empty (AE) flags synchronized by
CLKB
Passive parity checking on each Port
Parity Generation can be selected for each Port
Available in space-saving 120-pin Thin Quad Flatpack (PF)
Green parts available, see ordering information
DESCRIPTION:
TheIDT72V3611isdesignedtorunoffa3.3Vsupplyforexceptionallylow
power consumption. This device is a monolithic, high-speed, low-power,
CMOSSynchronous(clocked)FIFOmemorywhichsupportsclockfrequen-
ciesupto67MHzandhasreadaccesstimesasfastas10ns.The64 x 36dual-
portFIFObuffersdatafromPortAtoPortB.TheFIFOoperatesinIDTStandard
modeandhasflagstoindicateemptyandfullconditions,andtwoprogrammable
flags, Almost-Full (AF) and Almost-Empty (AE), to indicate when a selected
numberofwordsisstoredinmemory. Communicationbetweeneachportcan
take place through two 36-bit mailbox registers. Each mailbox register has a
flagtosignalwhen newmailhasbeenstored. Parityischeckedpassivelyon
eachportandmaybeignoredifnotdesired. Paritygenerationcanbeselected
FUNCTIONAL BLOCK DIAGRAM
Mail 2
Register
Mail 1
Register
Input
Register
Output
Register
Write
Pointer
Read
Pointer
Status Flag
Logic
CLKA
CSA
W/
RA
ENA
MBA
Port-A
Control
Logic
Reset
Logic
RST
PEFA
MBF2
CLKB
CSB
W/
RB
ENB
MBB
Port-B
Control
Logic
MBF1
EF
AE
36
B0 - B35
FF
AF
FS0
FS1
4657 drw01
Programmable
Flag Offset
Registers
A0 - A35
Parity
Gen/Check
Parity
Generation
FIFO
ODD/
EVEN
PGA
Parity
Gen/Check
PGB
PEFB
36
RAM
ARRAY
64 x 36
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相关代理商/技术参数 |
参数描述 |
|---|---|
| IDT72V3611L15PFG | 制造商:Integrated Device Technology Inc 功能描述:IC FIFO SYNC 64X36 15NS 120TQFP |
| IDT72V3611L15PFG8 | 制造商:Integrated Device Technology Inc 功能描述:IC FIFO SYNC 64X36 15NS 120TQFP |
| IDT72V3611L15PQF | 功能描述:IC FIFO SYNC 64X36 15NS 132-PQFP RoHS:否 类别:集成电路 (IC) >> 逻辑 - FIFO 系列:72V 标准包装:90 系列:7200 功能:同步 存储容量:288K（16K x 18） 数据速率:100MHz 访问时间:10ns 电源电压:4.5 V ~ 5.5 V 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:64-LQFP 供应商设备封装:64-TQFP（14x14） 包装:托盘 其它名称:72271LA10PF |
| IDT72V3611L20PF | 功能描述:IC FIFO SYNC 64X36 20NS 120-TQFP RoHS:否 类别:集成电路 (IC) >> 逻辑 - FIFO 系列:72V 标准包装:90 系列:7200 功能:同步 存储容量:288K（16K x 18） 数据速率:100MHz 访问时间:10ns 电源电压:4.5 V ~ 5.5 V 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:64-LQFP 供应商设备封装:64-TQFP（14x14） 包装:托盘 其它名称:72271LA10PF |
| IDT72V3611L20PF8 | 功能描述:IC FIFO SYNC 64X36 20NS 120-TQFP RoHS:否 类别:集成电路 (IC) >> 逻辑 - FIFO 系列:72V 标准包装:90 系列:7200 功能:同步 存储容量:288K（16K x 18） 数据速率:100MHz 访问时间:10ns 电源电压:4.5 V ~ 5.5 V 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:64-LQFP 供应商设备封装:64-TQFP（14x14） 包装:托盘 其它名称:72271LA10PF |
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