参数资料
型号: IDT72V3626L10PF
厂商: INTEGRATED DEVICE TECHNOLOGY INC
元件分类: FIFO
英文描述: 3.3 VOLT CMOS TRIPLE BUS SyncFIFO WITH BUS-MATCHING 256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2
中文描述: 256 X 36 BI-DIRECTIONAL FIFO, 6.5 ns, PQFP128
封装: TQFP-128
文件页数: 1/21页
文件大小: 374K
代理商: IDT72V3626L10PF
2001 Integrated Device Technology, Inc. All right reserved. Product specifications subject to change without notice.
DSC-4665/5
AUGUST 2001
3.3 VOLT CMOS TRIPLE BUS
SyncFIFOTM WITH BUS-MATCHING
256 x 36 x 2, 512 x 36 x 2,
1,024 x 36 x 2
IDT72V3626
IDT72V3636
IDT72V3646
1
IDT and the IDT logo are trademarks of Integrated Device Technology, Inc. SyncFIFO is a trademark of Integrated Device Technology, Inc.
COMMERCIAL TEMPERATURE RANGE
FUNCTIONAL BLOCK DIAGRAM
FEATURES:
Memory storage capacity:
IDT72V3626–256 x 36 x 2
IDT72V3636–512 x 36 x 2
IDT72V3646–1,024 x 36 x 2
Clock frequencies up to 100 MHz (6.5ns access time)
Two independent FIFOs buffer data between one bidirectional
36-bit port and two unidirectional 18-bit ports (Port C receives
and Port B transmits)
18-bit (word) and 9-bit (byte) bus sizing of 18 bits (word) on
Ports B and C
Select IDT Standard timing (using EFA, EFB, FFA, and FFC flag
functions) or First Word Fall Through Timing (using ORA, ORB,
IRA, and IRC flag functions)
Programmable Almost-Empty and Almost-Full flags; each has
three default offsets (8, 16 and 64)
Serial or parallel programming of partial flags
Big- or Little-Endian format for word and byte bus sizes
Master Reset clears data and configures FIFO, Partial Reset
clears data but retains configuration settings
Mailbox bypass registers for each FIFO
Free-running CLKA, CLKB and CLKC may be asynchronous or
coincident (simultaneous reading and writing of data on a single
clock edge is permitted)
Auto power down minimizes power dissipation
Available in a space-saving 128-pin Thin Quad Flatpack (TQFP)
Pin and functionally compatible versions of 5V operating
IDT723626/723636/723646
Industrial temperature range (–40
°°°°°C to +85°°°°°C) is available
Mail 1
Register
Programmable Flag
Offset Registers
Input
Register
RAM ARRAY
256 x 36
512 x 36
1,024 x 36
Write
Pointer
Read
Pointer
Status Flag
Logic
Input
Register
Output
Register
RAM ARRAY
256 x 36
512 x 36
1,024 x 36
Write
Pointer
Read
Pointer
Status Flag
Logic
CLKA
CSA
W/
RA
ENA
MBA
Port-A
Control
Logic
FIFO1,
Mail1
Reset
Logic
MRS1
Mail 2
Register
MBF2
WENC
Port-C
Control
Logic
FIFO2,
Mail2
Reset
Logic
MRS2
MBF1
FIFO1
FIFO2
10
EFB/ORB
AEB
18
FFC/IRC
AFC
B0-B17
FFA/IRA
AFA
SPM
FS0/SD
FS1/
SEN
A0-A35
EFA/ORA
AEA
4665 drw01
36
Output
Bus-
Matching
Output
Register
PRS2
PRS1
Timing
Mode
FWFT
C0-C17
CLKB
RENB
CSB
MBB
Port-B
Control
Logic
Common
Port
Control
Logic
(B and C)
BE
SIZEB
SIZEC
CLKC
MBC
36
Input
Bus-
Matching
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