参数资料
型号: IDT72V3670L6PF8
厂商: IDT, Integrated Device Technology Inc
文件页数: 10/46页
文件大小: 0K
描述: IC FIFO SS 8192X36 6NS 128-TQFP
标准包装: 1,000
系列: 72V
功能: 异步,同步
存储容量: 288K(8K x 36)
数据速率: 166MHz
访问时间: 4ns
电源电压: 3.15 V ~ 3.45 V
工作温度: 0°C ~ 70°C
安装类型: 表面贴装
封装/外壳: 128-LQFP
供应商设备封装: 128-TQFP(14x20)
包装: 带卷 (TR)
其它名称: 72V3670L6PF8
18
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72V3640/50/60/70/80/90 3.3V HIGH DENSITY SUPERSYNC IITM 36-BIT FIFO
1,024 x 36, 2,048 x 36, 4,096 x 36, 8,192 x 36, 16,384 x 36 and 32,768 x 36
OCTOBER 22, 2008
if
EF was HIGH before setup. During this period, the internal read pointer is
initialized to the first location of the RAM array.
When
EF goes HIGH, Retransmit setup is complete and read operations
may begin starting with the first location in memory. Since IDT Standard mode
is selected, every word read including the first word following Retransmit setup
requires a LOW on
REN to enable the rising edge of RCLK. See Figure 11,
Retransmit Timing (IDT Standard Mode), for the relevant timing diagram.
IfFWFTmodeisselected,theFIFOwillmarkthebeginningoftheRetransmit
setup by setting
OR HIGH. During this period, the internal read pointer is set
to the first location of the RAM array.
When
ORgoesLOW,Retransmitsetupiscomplete;atthesametime,the
contentsofthefirstlocationappearontheoutputs. SinceFWFTmodeisselected,
the first word appears on the outputs, no LOW on
RENisnecessary.Reading
all subsequent words requires a LOW on
REN to enable the rising edge of
RCLK.SeeFigure12,RetransmitTiming(FWFTMode),fortherelevanttiming
diagram.
For either IDT Standard mode or FWFT mode, updating of the
PAE, HF
and
PAF flags begin with the rising edge of RCLK that RT is setup. PAE is
synchronizedtoRCLK,thusonthesecondrisingedgeofRCLKafter
RTissetup,
the
PAEflagwillbeupdated. HFisasynchronous,thustherisingedgeofRCLK
that
RTissetupwillupdateHF. PAFissynchronizedtoWCLK,thusthesecond
rising edge of WCLK that occurs tSKEW after the rising edge of RCLK that
RT
is setup will update
PAF. RT is synchronized to RCLK.
The Retransmit function has the option of two modes of operation, either
“normal latency” or “zero latency”. Figure 11 and Figure 12 mentioned
previously, relate to “normal latency”. Figure 13 and Figure 14 show “zero
latency” retransmit operation. Zero latency basically means that the first data
word to be retransmitted, is placed onto the output register with respect to the
RCLK pulse that initiated the retransmit.
相关PDF资料
PDF描述
IDT72V3670L6BB8 IC FIFO SS 8192X36 6NS 144-BGA
V72B36M250BG CONVERTER MOD DC/DC 36V 250W
IDT72T1865L5BB IC FIFO 8192X18 5NS 144BGA
HIN232CBZ-T IC 2DRVR/2RCVR RS232 5V 16-SOIC
HIN202IBNZ IC 2DRVR/2RCVR RS232 5V 16-SOIC
相关代理商/技术参数
参数描述
IDT72V3670L6PFG 功能描述:IC FIFO 8192X36 SYNC 6NS 128TQFP RoHS:是 类别:集成电路 (IC) >> 逻辑 - FIFO 系列:72V 标准包装:15 系列:74F 功能:异步 存储容量:256(64 x 4) 数据速率:- 访问时间:- 电源电压:4.5 V ~ 5.5 V 工作温度:0°C ~ 70°C 安装类型:通孔 封装/外壳:24-DIP(0.300",7.62mm) 供应商设备封装:24-PDIP 包装:管件 其它名称:74F433
IDT72V3670L6PFG8 制造商:Integrated Device Technology Inc 功能描述:IC FIFO SS 8192X36 6NS 128-TQFP
IDT72V3670L7-5BB 功能描述:IC FIFO SS 8192X36 7-5NS 144BGA RoHS:否 类别:集成电路 (IC) >> 逻辑 - FIFO 系列:72V 标准包装:15 系列:74F 功能:异步 存储容量:256(64 x 4) 数据速率:- 访问时间:- 电源电压:4.5 V ~ 5.5 V 工作温度:0°C ~ 70°C 安装类型:通孔 封装/外壳:24-DIP(0.300",7.62mm) 供应商设备封装:24-PDIP 包装:管件 其它名称:74F433
IDT72V3670L7-5BB8 功能描述:IC FIFO SS 8192X36 7-5NS 144BGA RoHS:否 类别:集成电路 (IC) >> 逻辑 - FIFO 系列:72V 标准包装:90 系列:7200 功能:同步 存储容量:288K(16K x 18) 数据速率:100MHz 访问时间:10ns 电源电压:4.5 V ~ 5.5 V 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:64-LQFP 供应商设备封装:64-TQFP(14x14) 包装:托盘 其它名称:72271LA10PF
IDT72V3670L7-5BBI 功能描述:IC FIFO SS 8192X36 7-5NS 144BGA RoHS:否 类别:集成电路 (IC) >> 逻辑 - FIFO 系列:72V 标准包装:15 系列:74F 功能:异步 存储容量:256(64 x 4) 数据速率:- 访问时间:- 电源电压:4.5 V ~ 5.5 V 工作温度:0°C ~ 70°C 安装类型:通孔 封装/外壳:24-DIP(0.300",7.62mm) 供应商设备封装:24-PDIP 包装:管件 其它名称:74F433