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参数资料
| 型号： | IDT72V3690L6BB |
| 厂商： | IDT, Integrated Device Technology Inc |
| 文件页数： | 5/46页 |
| 文件大小： | 0K |
| 描述： | IC FIFO SS 32768X36 6NS 144-BGA |
| 标准包装： | 1 |
| 系列： | 72V |
| 功能： | 异步，同步 |
| 存储容量： | 1.1M（32K x 36） |
| 数据速率： | 166MHz |
| 访问时间： | 4ns |
| 电源电压： | 3.15 V ~ 3.45 V |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 144-BGA |
| 供应商设备封装： | 144-PBGA（13x13） |
| 包装： | 托盘 |
| 其它名称： | 72V3690L6BB |
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13
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72V3640/50/60/70/80/90 3.3V HIGH DENSITY SUPERSYNC IITM 36-BIT FIFO
1,024 x 36, 2,048 x 36, 4,096 x 36, 8,192 x 36, 16,384 x 36 and 32,768 x 36
OCTOBER 22, 2008
PROGRAMMING FLAG OFFSETS
FullandEmptyFlagoffsetvaluesareuserprogrammable.TheIDT72V3640/
72V3650/72V3660/72V3670/72V3680/72V3690 have internal registers for
these offsets. There are eight default offset values selectable during Master
Reset. These offset values are shown in Table 2. Offset values can also be
programmedintotheFIFOinoneoftwoways;serialorparallelloadingmethod.
The selection of the loading method is done using the
LD (Load) pin. During
MasterReset,thestateofthe
LDinputdetermineswhetherserialorparallelflag
offsetprogrammingisenabled. AHIGHon
LDduringMasterResetselectsserial
loading of offset values. A LOW on
LD during Master Reset selects parallel
loading of offset values.
In addition to loading offset values into the FIFO, it is also possible to read
the current offset values. Offset values can be read via the parallel output port
Q0-Qn, regardless of the programming mode selected (serial or parallel). It is
not possible to read the offset values in serial fashion.
Figure 3, Programmable Flag Offset Programming Sequence, summaries
thecontrolpinsandsequenceforbothserialandparallelprogrammingmodes.
For a more detailed description, see discussion that follows.
Theoffsetregistersmaybeprogrammed(andreprogrammed)anytimeafter
Master Reset, regardless of whether serial or parallel programming has been
selected. Valid programming ranges are from 0 to D-1.
SYNCHRONOUS vs ASYNCHRONOUS PROGRAMMABLE FLAG
TIMING SELECTION
The IDT72V3640/72V3650/72V3660/72V3670/72V3680/72V3690 can
be configured during the Master Reset cycle with either synchronous or
asynchronous timing for
PAF and PAE flags by use of the PFM pin.
If synchronous
PAF/PAE configuration is selected (PFM, HIGH during
MRS), the PAF is asserted and updated on the rising edge of WCLK only and
not RCLK. Similarly,
PAEisassertedandupdatedontherisingedgeofRCLK
only and not WCLK. For detail timing diagrams, see Figure 17 for synchronous
PAF timing and Figure 18 for synchronous PAE timing.
If asynchronous
PAF/PAE configuration is selected (PFM, LOW during
MRS),thePAFisassertedLOWontheLOW-to-HIGHtransitionofWCLKand
PAFisresettoHIGHontheLOW-to-HIGHtransitionofRCLK. Similarly,PAE
isassertedLOWontheLOW-to-HIGHtransitionofRCLK.
PAEisresettoHIGH
ontheLOW-to-HIGHtransitionofWCLK.Fordetailtimingdiagrams,seeFigure
19 for asynchronous
PAFtimingandFigure20forasynchronousPAEtiming.
IDT72V3640, 72V3650
LD
FSEL1
FSEL0
Offsets n,m
LH
L
511
L
H
255
L
127
LH
H
63
HL
L
31
HH
L
15
HL
H
7
HH
H
3
LD
FSEL1
FSEL0
Program Mode
H
X
Serial(3)
L
X
Parallel(4)
IDT72V3660, 72V3670, 72V3680, 72V3690
LD
FSEL1
FSEL0
Offsets n,m
H
L
1,023
LH
L
511
L
H
255
L
127
LH
H
63
HH
L
31
HL
H
15
HH
H
7
LD
FSEL1
FSEL0
Program Mode
H
X
Serial(3)
L
X
Parallel(4)
TABLE 2 — DEFAULT PROGRAMMABLE
FLAG OFFSETS
NOTES:
1. n = empty offset for
PAE.
2. m = full offset for
PAF.
3. As well as selecting serial programming mode, one of the default values will also
be loaded depending on the state of FSEL0 & FSEL1.
4. As well as selecting parallel programming mode, one of the default values will
also be loaded depending on the state of FSEL0 & FSEL1.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| IDT72V3690L6BB8 | 功能描述:IC FIFO SS 32768X36 6NS 144-BGA RoHS:否 类别:集成电路 (IC) >> 逻辑 - FIFO 系列:72V 标准包装:15 系列:74F 功能:异步 存储容量:256（64 x 4） 数据速率:- 访问时间:- 电源电压:4.5 V ~ 5.5 V 工作温度:0°C ~ 70°C 安装类型:通孔 封装/外壳:24-DIP（0.300"，7.62mm） 供应商设备封装:24-PDIP 包装:管件 其它名称:74F433 |
| IDT72V3690L6BBG | 制造商:Integrated Device Technology Inc 功能描述:IC FIFO SS 32768X36 6NS 144-BGA |
| IDT72V3690L6BBG8 | 制造商:Integrated Device Technology Inc 功能描述:IC FIFO SS 32768X36 6NS 144-BGA |
| IDT72V3690L6PF | 功能描述:IC FIFO SS 32768X36 6NS 128-TQFP RoHS:否 类别:集成电路 (IC) >> 逻辑 - FIFO 系列:72V 标准包装:15 系列:74F 功能:异步 存储容量:256（64 x 4） 数据速率:- 访问时间:- 电源电压:4.5 V ~ 5.5 V 工作温度:0°C ~ 70°C 安装类型:通孔 封装/外壳:24-DIP（0.300"，7.62mm） 供应商设备封装:24-PDIP 包装:管件 其它名称:74F433 |
| IDT72V3690L6PF8 | 功能描述:IC FIFO SS 32768X36 6NS 128-TQFP RoHS:否 类别:集成电路 (IC) >> 逻辑 - FIFO 系列:72V 标准包装:15 系列:74F 功能:异步 存储容量:256（64 x 4） 数据速率:- 访问时间:- 电源电压:4.5 V ~ 5.5 V 工作温度:0°C ~ 70°C 安装类型:通孔 封装/外壳:24-DIP（0.300"，7.62mm） 供应商设备封装:24-PDIP 包装:管件 其它名称:74F433 |
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