参数资料
型号: IDT72V51236L6BB
厂商: IDT, Integrated Device Technology Inc
文件页数: 48/56页
文件大小: 0K
描述: IC FLOW CTRL MULTI QUEUE 256-BGA
标准包装: 1
类型: 多队列流量控制
安装类型: 表面贴装
封装/外壳: 256-BBGA
供应商设备封装: 256-BGA(17x17)
包装: 托盘
其它名称: 72V51236L6BB
52
IDT72V51236/72V51246/72V51256 3.3V, MULTI-QUEUE FLOW-CONTROL DEVICES
(4 QUEUES) 36 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
Test-Logic
Reset
Run-Test/
Idle
1
0
Select-
DR-Scan
Select-
IR-Scan
1
Capture-IR
0
Capture-DR
0
Exit1-DR
1
Pause-DR
0
Exit2-DR
1
Update-DR
1
Exit1-IR
1
Exit2-IR
1
Update-IR
1
0
1
5937 drw35
0
Shift-DR
0
Shift-IR
0
Pause-IR
0
1
Input = TMS
0
1
Refer to the IEEE Standard Test Access Port Specification (IEEE Std.
1149.1) for the full state diagram
All state transitions within the TAP controller occur at the rising edge of the
TCLK pulse. The TMS signal level (0 or 1) determines the state progression
that occurs on each TCLK rising edge. The TAP controller takes precedence
over the Queue and must be reset after power up of the device. See
TRST
description for more details on TAP controller reset.
Test-Logic-Reset All test logic is disabled in this controller state enabling
the normal operation of the IC. The TAP controller state machine is designed
in such a way that, no matter what the initial state of the controller is, the Test-
Logic-Reset state can be entered by holding TMS at high and pulsing TCK five
times. This is the reason why the Test Reset (
TRST) pin is optional.
Run-Test-Idle In this controller state, the test logic in the IC is active only if
certaininstructionsarepresent.Forexample,ifaninstructionactivatestheself
test, then it will be executed when the controller enters this state. The test logic
in the IC is idles otherwise.
Select-DR-Scan This is a controller state where the decision to enter the
Data Path or the Select-IR-Scan state is made.
Select-IR-Scan This is a controller state where the decision to enter the
InstructionPathismade.TheControllercanreturntotheTest-Logic-Resetstate
other wise.
Figure 32. TAP Controller State Diagram
Capture-IR In this controller state, the shift register bank in the Instruction
Register parallel loads a pattern of fixed values on the rising edge of TCK. The
last two significant bits are always required to be “01”.
Shift-IR In this controller state, the instruction register gets connected
betweenTDIandTDO,andthecapturedpatterngetsshiftedoneachrisingedge
ofTCK.TheinstructionavailableontheTDIpinisalsoshiftedintotheinstruction
register.
Exit1-IRThisisacontrollerstatewhereadecisiontoentereitherthePause-
IR state or Update-IR state is made.
Pause-IR This state is provided in order to allow the shifting of instruction
register to be temporarily halted.
Exit2-DR This is a controller state where a decision to enter either the Shift-
IR state or Update-IR state is made.
Update-IR In this controller state, the instruction in the instruction register is
latched in to the latch bank of the Instruction Register on every falling edge of
TCK. This instruction also becomes the current instruction once it is latched.
Capture-DR In this controller state, the data is parallel loaded in to the data
registers selected by the current instruction on the rising edge of TCK.
Shift-DR, Exit1-DR, Pause-DR, Exit2-DR and Update-DR These
controller states are similar to the Shift-IR, Exit1-IR, Pause-IR, Exit2-IR and
Update-IR states in the Instruction path.
NOTES:
1. Five consecutive TCK cycles with TMS = 1 will reset the TAP.
2. TAP controller does not automatically reset upon power-up. The user must provide a reset to the TAP controller (either by
TRST or TMS).
3. TAP controller must be reset before normal Queue operations can begin.
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