参数资料
型号: IDT72V51433L6BB
厂商: IDT, Integrated Device Technology Inc
文件页数: 14/50页
文件大小: 0K
描述: IC FLOW CTRL MULTI QUEUE 256-BGA
标准包装: 1
类型: 多队列流量控制
安装类型: 表面贴装
封装/外壳: 256-BBGA
供应商设备封装: 256-BGA(17x17)
包装: 托盘
其它名称: 72V51433L6BB
21
IDT72V51433/72V51443/72V51453 3.3V, MULTI-QUEUE FLOW-CONTROL DEVICES
(16 QUEUES) 18 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
within a queue can be at any point within that queues depth. This location can
be user programmed via the serial port or one of the default values (8 or 128)
can be selected if the user has performed default programming.
As mentioned, every queue within a multi-queue device has its own almost
emptystatus,whenaqueueisselectedonthereadport,thisstatusisoutputvia
the
PAEflag.ThePAEflagvalueforeachqueueisprogrammedduringmulti-
queue device programming (along with the number of queues, queue depths
and almost full values). The
PAEoffsetvalue,n,forarespectivequeuecanbe
programmedtobeanywherebetween‘0’and‘D’,where‘D’isthetotalmemory
depthforthatqueue.The
PAEvalueofdifferentqueueswithinthesamedevice
can be different values.
When queue switches are being made on the read port, the
PAEflagoutput
will switch to the new queue and provide the user with the new queue status,
on the second cycle after a new queue selection is made, on the same RCLK
cycle that data actually falls through to the output register from the new queue.
That is, a new queue can be selected on the read port via the RDADD bus,
RADENenableandarisingedgeofRCLK.OnthesecondrisingedgeofRCLK
followingaqueueselection,thedatawordfromthenewqueuewillbeavailable
at the output register and the
PAEflagoutputwillshowtheemptystatusofthe
newly selected queue. The
PAE is flag output is double register buffered, so
when a read operation occurs at the almost empty boundary causing the
selected queue status to go almost empty the
PAEwillgoLOW2RCLKcycles
after the read. The same is true when a write occurs, there will be a 2 RCLK
cycle delay after the write operation.
So the
PAE flag delays are:
from a read operation to
PAE flag LOW is 2 RCLK + tRAE
The delay from a write operation to
PAEflagHIGHistSKEW2+RCLK+tRAE
Note, if tSKEW is violated there will be one added RCLK cycle delay.
The
PAEflagissynchronoustotheRCLKandalltransitionsofthePAEflag
occur based on a rising edge of RCLK. Internally the multi-queue device
monitorsandkeepsarecordofthealmostemptystatusforallqueues.Itispossible
that the status of a
PAEflagmaybechanginginternallyeventhoughthatflagis
not the active queue flag (selected on the read port). A queue selected on the
writeportmayexperienceachangeofitsinternalalmostemptyflagstatusbased
on write operations. The multi-queue flow-control device also provides a
duplicateofthe
PAEflagonthePAE[7:0]flagbus,thiswillbediscussedindetail
in a later section of the data sheet.
See Figures 20 and 21 for Almost Empty flag timing and queue switching.
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