参数资料
型号: IDT72V51443L7-5BB8
厂商: IDT, Integrated Device Technology Inc
文件页数: 10/50页
文件大小: 0K
描述: IC FLOW CTRL MULTI QUEUE 256-BGA
标准包装: 1,000
类型: 多队列流量控制
安装类型: 表面贴装
封装/外壳: 256-BBGA
供应商设备封装: 256-BGA(17x17)
包装: 带卷 (TR)
其它名称: 72V51443L7-5BB8
18
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72V51433/72V51443/72V51453 3.3V, MULTI-QUEUE FLOW-CONTROL DEVICES
(16 QUEUES) 18 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits
READ QUEUE SELECTION & READ OPERATION
The multi-queue flow-control device has up to 16 queues that data is read
from via a common read port using the data outputs, Qout, read clock, RCLK
andreadenable,
REN.Anoutputenable,OEcontrolpinisalsoprovidedtoallow
High-Impedance selection of the Qout data outputs. The multi-queue device
readportoperatesinamodesimilarto“FirstWordFallThrough”onatraditional
IDT FIFO, but with the added feature of data output pipelining. This data
pipelining on the output port allows the user to achieve 100% bus utilization,
which is the ability to read out a data word on every rising edge of RCLK
regardless of whether a new queue is being selected for read operations.
Thequeueaddresspresentonthereadaddressbus,RDADDduringarising
edge on RCLK while read address enable, RADEN is HIGH, is the queue
selected for read operations. A queue to be read from need only be selected
on a single rising edge of RCLK. All subsequent reads will be read from that
queue until a new queue is selected. A minimum of 2 RCLK cycles must occur
betweenqueueselectionsonthereadport.Datafromthenewlyselectedqueue
will be present on the Qout outputs after 2 RCLK cycles plus an access time,
provided that
OE isactive,LOW.OnthesameRCLKrisingedgethatthenew
queue is selected, data can still be read from the previously selected queue,
provided that
REN isLOW,activeandthepreviousqueueisnotemptyonthe
following rising edge of RCLK a word will be read from the previously selected
queueregardlessof
RENduetothefallthroughoperation,(providedthequeue
isnotempty). Rememberthat
OEallowstheusertoplacetheQout,dataoutput
bus into High-Impedance and the data can be read onto the output register
regardless of
OE.
When a queue is selected on the read port, the next word available in that
queue (provided that the queue is not empty), will fall through to the output
register after 2 RCLK cycles. As mentioned, in the previous 2 RCLK cycles to
the new data being available, data can still be read from the previous queue,
providedthatthequeueisnotempty.Atthepointofqueueselection,the2-stage
internal data pipeline is loaded with the last word from the previous queue and
thenextwordfromthenewqueue,boththesewordswillfallthroughtotheoutput
register consecutively upon selection of the new queue. This pipelining effect
provides the user with 100% bus utilization, but brings about the possibility that
a “NULL” queue may be required within a multi-queue device. Null queue
operation is discussed in the next section on.
IfanemptyqueueisselectedforreadoperationsontherisingedgeofRCLK,
onthesameRCLKedgeandthefollowingRCLKedge,2finalreadswillbemade
from the previous queue, provided that
RENisactive,LOW.OnthenextRCLK
rising edge a read from the new queue will not occur, because the queue is
empty. The last word in the data output register (from the previous queue), will
remain there, but the output valid flag,
OVwillgoHIGH,toindicatethatthedata
present is no longer valid.
The RDADD bus is also used in conjunction with ESTR (almost empty flag
bus strobe), to address the almost empty flag bus of a respective device during
direct mode of operation. In the 16 queue multi-queue device the RDADD
address bus is 8 bits wide. The least significant 4 bits are used to address one
of the 16 available queues within a single multi-queue device. The 5th least
significant bit is used to select a "Null" Queue. During a Null-Q selection the 4
LSB's are don't care. The Null-Q is seen as an empty queue on the read port.
Null-Q operation is discussed in more detail in a separate section. The most
significant 3 bits are used when a device is connected in expansion mode, up
to 8 devices can be connected in expansion, each device having its own 3 bit
address. The selected device is the one for which the address matches a 3 bit
ID code, which is statically setup on the ID pins, ID0, ID1, and ID2 of each
individual device.
Refer to Table 2, for Read Address bus arrangement. Also, refer to Figures
12,14 & 15 for read queue selection and read port operation timing diagrams.
Operation RCLK
RADEN
ESTR
RDADD[7:0]
Read Queue
Select
10
01
Device Select
(Compared to
ID0,1,2)
Read Queue Address
(4 bits = 16 Queues)
7
6
5
4
3210
4 321
0
Device Select
(Compared to
ID0,1,2)
X X X
Sector
Address
PAEn Sector
Select
Q0 : Q7
→ PAE0 : PAE7
Sector
Address
Queue Status on
PAEn Bus
0
1
Q8 : Q15
→ PAE0 : PAE7
5939 drw06
X
Null-Q
Select
Pin
TABLE 2 — READ ADDRESS BUS, RDADD[7:0]
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