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| 型号： | IDT72V51453L7-5BB |
| 厂商： | IDT, Integrated Device Technology Inc |
| 文件页数： | 2/50页 |
| 文件大小： | 0K |
| 描述： | IC FLOW CTRL MULTI QUEUE 256-BGA |
| 标准包装： | 1 |
| 类型： | 多队列流量控制 |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 256-BBGA |
| 供应商设备封装： | 256-BGA（17x17） |
| 包装： | 托盘 |
| 其它名称： | 72V51453L7-5BB |
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10
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72V51433/72V51443/72V51453 3.3V, MULTI-QUEUE FLOW-CONTROL DEVICES
(16 QUEUES) 18 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits
PIN DESCRIPTIONS (CONTINUED)
Symbol
Name
I/O TYPE
Description
RDADD
Read Address Bus
LVTTL
data can be placed on to the Qout bus, read from the previously selected queue on this RCLK edge). On
[7:0]
INPUT
the next rising RCLK edge after a read queue select, a data word from the previous queue will be placed
(Continued)
ontotheoutputs,Qout,regardlessofthe
RENinput.TwoRCLKrisingedgesafterreadqueueselect,data
will be placed on to the Qout outputs from the newly selected queue, regardless of
REN due to the first
word fall through effect.
The second function of the RDADD bus is to select the sector of queues to be loaded on to the
PAEnbus
during strobed flag mode. The least significant bit, RDADD[0] is used to select the sector of a device to
be placed on the
PAEn bus. The most significant 3 bits, RDADD[7:5] are again used to select 1 of 8
possible multi-queue devices that may be connected in expansion mode. Address bits RDADD[4:2] are
don’t care during sector selection. The sector address present on the RDADD bus will be selected on the
rising edge of RCLK provided that ESTR is HIGH, (note, that data can be placed on to the Qout bus, read
fromthepreviouslyselectedqueueonthisRCLKedge).PleaserefertoTable2fordetailsonRDADDbus.
REN
Read Enable
LVTTL
The
REN input enables read operations from a selected queue based on a rising edge of RCLK. A
INPUT
queue to be read from can be selected via RCLK, RADEN and the RDADD address bus regardless
ofthestateof
REN.DatafromanewlyselectedqueuewillbeavailableontheQoutoutputbusonthesecond
RCLK cycle after queue selection regardless of
REN due to the FWFT operation. A read enable is not
required to cycle the
PAEn bus (in polled mode) or to select the PAEn sector , (in direct mode).
SCLK
Serial Clock
LVTTL
If serial programming of the multi-queue device has been selected during master reset, the SCLK input
INPUT
clocks the serial data through the multi-queue device. Data setup on the SI input is loaded into the device
ontherisingedgeofSCLKprovidedthat
SENIisenabled,LOW.Whenexpansionofdevicesisperformed
the SCLK of all devices should be connected to the same source.
SENI
Serial Input Enable
LVTTL
During serial programming of a multi-queue device, data loaded onto the SI input will be clocked into the
INPUT
part (via a rising edge of SCLK), provided the
SENI input of that device is LOW. If multiple devices are
cascaded,the
SENIinputshouldbeconnectedtotheSENOoutputofthepreviousdevice.Sowhenserial
loading of a given device is complete, its
SENO output goes LOW, allowing the next device in the chain
to be programmed (
SENOwillfollowSENIofagivendeviceoncethatdeviceisprogrammed).TheSENI
input of the master device (or single device), should be controlled by the user.
SENO
Serial Output Enable
LVTTL
This output is used to indicate that serial programming or default programming of the multi-queue device
OUTPUT
has been completed.
SENOfollowsSENIonceprogrammingofadeviceiscomplete.Therefore,SENO
will go LOW after programming provided
SENIisLOW,onceSENI istakenHIGHagain,SENOwillalso
go HIGH. When the
SENOoutputgoesLOW,thedeviceisreadytobeginnormalread/writeoperations.
If multiple devices are cascaded and serial programming of the devices will be used, the
SENO output
should be connected to the
SENI input of the next device in the chain. When serial programming of the
first device is complete,
SENO will go LOW, thereby taking the SENI input of the next device LOW and
so on throughout the chain. When a given device in the chain is fully programmed the
SENO output
essentiallyfollowsthe
SENIinput.TheusershouldmonitortheSENOoutputofthefinaldeviceinthechain.
When this output goes LOW, serial loading of all devices has been completed.
SI
Serial In
LVTTL
Duringserialprogrammingthispinisloadedwiththeserialdatathatwillconfigurethemulti-queuedevices.
INPUT
Data present on SI will be loaded on a rising edge of SCLK provided that
SENI is LOW. In expansion
modetheserialdatainputisloadedintothefirstdeviceinachain.Whenthatdeviceisloadedandits
SENO
hasgoneLOW,thedatapresentonSIwillbedirectlyoutputtotheSOoutput.TheSOpinofthefirstdevice
connects to the SI pin of the second and so on. The multi-queue device setup registers are shift registers.
SO
Serial Out
LVTTL
This output is used in expansion mode and allows serial data to be passed through devices in the chain
OUTPUT
to complete programming of all devices. The SI of a device connects to SO of the previous device in the
chain. The SO of the final device in a chain should not be connected.
TCK(2)
JTAG Clock
LVTTL
Clock input for JTAG function. One of four terminals required by IEEE Standard 1149.1-1990. Test
INPUT
operationsofthedevicearesynchronoustoTCK.DatafromTMSandTDIaresampledontherisingedge
of TCK and outputs change on the falling edge of TCK. If the JTAG function is not used this signal needs
to be tied to GND.
TDI(2)
JTAG Test Data
LVTTL
One of four terminals required by IEEE Standard 1149.1-1990. During the JTAG boundary scan
Input
INPUT
operation, test data serially loaded via the TDI on the rising edge of TCK to either the Instruction Register,
ID Register and Bypass Register. An internal pull-up resistor forces TDI HIGH if left unconnected.
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| IDT72V51453L7-5BB8 | 功能描述:IC FLOW CTRL MULTI QUEUE 256-BGA RoHS:否 类别:集成电路 (IC) >> 专用 IC 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:1 系列:- 类型:调帧器 应用:数据传输 安装类型:表面贴装 封装/外壳:400-BBGA 供应商设备封装:400-PBGA（27x27） 包装:散装 |
| IDT72V51453L7-5BBI | 功能描述:IC FLOW CTRL MULTI QUEUE 256-BGA RoHS:否 类别:集成电路 (IC) >> 专用 IC 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:1 系列:- 类型:调帧器 应用:数据传输 安装类型:表面贴装 封装/外壳:400-BBGA 供应商设备封装:400-PBGA（27x27） 包装:散装 |
| IDT72V51456L6BB | 功能描述:IC FLOW CTRL MULTI QUEUE 256-BGA RoHS:否 类别:集成电路 (IC) >> 专用 IC 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:1 系列:- 类型:调帧器 应用:数据传输 安装类型:表面贴装 封装/外壳:400-BBGA 供应商设备封装:400-PBGA（27x27） 包装:散装 |
| IDT72V51456L6BB8 | 功能描述:IC FLOW CTRL MULTI QUEUE 256-BGA RoHS:否 类别:集成电路 (IC) >> 专用 IC 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:1 系列:- 类型:调帧器 应用:数据传输 安装类型:表面贴装 封装/外壳:400-BBGA 供应商设备封装:400-PBGA（27x27） 包装:散装 |
| IDT72V51456L7-5BB | 功能描述:IC FLOW CTRL MULTI QUEUE 256-BGA RoHS:否 类别:集成电路 (IC) >> 专用 IC 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:1 系列:- 类型:调帧器 应用:数据传输 安装类型:表面贴装 封装/外壳:400-BBGA 供应商设备封装:400-PBGA（27x27） 包装:散装 |
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