参数资料
型号: IDT72V71623BCG
厂商: IDT, Integrated Device Technology Inc
文件页数: 24/28页
文件大小: 0K
描述: IC DGTL SW 2048X2048 144-BGA
标准包装: 14
系列: 72V
类型: 多路复用器
电路: 1 x 1:16
独立电路: 1
电压电源: 单电源
电源电压: 3 V ~ 3.6 V
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 144-LBGA
供应商设备封装: 144-CABGA(13x13)
包装: 托盘
其它名称: 72V71623BCG
5
COMMERCIAL TEMPERATURE RANGE
IDT72V71623 3.3V TIME SLOT INTERCHANGE
DIGITAL SWITCH 2,048 x 2,048
DESCRIPTION (CONTINUED)
Outputenableindicationsareprovidedthroughdedicatedpins(onepinper
outputstream)tofacilitateexternaldatabuscontrol.
The IDT72V71623 is capable of switching up to 2,048 x 2,048 channels
withoutblocking. Designedtoswitch64Kbit/sPCMorNx64Kbit/sdata,the
devicemaintainsframeintegrityindataapplicationsandminimizesthroughput
delay for voice applications on a per channel basis.
The serial input streams (RX) and serial output streams (TX) of the
IDT72V71623canberunupto16.384Mb/sallowing256channelsper125
s
frame. Depending on the input and output data rates the device can support
up to 16 serial streams.
Withtwomainoperatingmodes,ProcessormodeandConnectionMode,
theIDT72V71623caneasilyswitchdatafromincomingserialstreams(Data
Memory) or from the controlling microprocessor (Connection Memory). As
controlandstatusinformationiscriticalindatatransmission,theProcessormode
isespeciallyusefulwhentherearemultipledevicessharingtheinputandoutput
streams.
With two main configuration modes, Regular and Mux/Demux mode the
IDT72V71623isdesignedtoworkinamixeddata-rateenvironment. InMux/
Demuxmode,alloftheinputstreamsworkatonedatarateandtheoutputstreams
atanother. Dependingontheconfiguration,moreorlessserialstreamswillbe
availableontheinputsoroutputstomaintainanon-blockingswitch.
Withdatacomingfrommultiplesourcesandthroughdifferentpaths,data
enteringthedeviceisoftendelayed.Tohandlethisproblem,theIDT72V71623
hasaframeevaluationfeaturetoallowindividualstreamstobeoffsetfromthe
framepulseinhalfclock-cycleintervalsupto+4.5clockcyclesforspeedsup
to8Mb/sor+2.5clockcyclesfor16Mb/s.(SeeTable8formaximumallowable
skew).
The IDT72V71623 also provides a JTAG test access port, an internal
loopback feature, memory block programming, a simple microprocessor
interface and automatic ST-BUS/GCI sensing to shorten setup time, aid in
debuggingandeaseuseofthedevicewithoutsacrificingcapabilities.
FUNCTIONALDESCRIPTION
DATAANDCONNECTIONMEMORY
AlldatathatcomesinthroughtheRXinputsgothroughaserial-to-parallel
conversion before being stored into internal Data Memory. The 8 KHz frame
pulse (F0i) is used to mark the 125
s frame boundaries and to sequentially
addresstheinputchannelsinDataMemory. TheDataMemoryisonlywritten
bythedevicefromtheRXstreamsandcanbereadfromeithertheTXstreams
orthemicroprocessor.
DataoutputontheTXstreamsmaycomefromeithertheSerialInputStreams
(DataMemory)orfromthemicroprocessor(ConnectionMemory).Inthecase
thatRXinputdataistobeoutput,theaddressesinConnectionMemoryareused
tospecifyastreamandchanneloftheinput.TheConnectionMemoryissetup
in such a way that each location corresponds to an output channel for each
particularstream.Inthatway,morethanonechannelcanoutputthesamedata.
InProcessormode,themicroprocessorwritesdatatotheConnectionMemory
locationscorrespondingtothestreamandchannelthatistobeoutput.Thelower
byte(8leastsignificantbits)oftheConnectionMemoryisoutputeveryframe
untilthemicroprocessorchangesthedataormodeofthechannel.Byusingthis
Processormodecapability,themicroprocessorcanaccessinputandoutput
time-slotsonaperchannelbasis.
ThemostsignificantbitsoftheConnectionMemoryareusedtocontrolper
channelfunctionssuchasProcessormode,ConstantorVariableDelaymode,
three-stateofoutputdrivers,andtheLoopbackfunction.
OPERATINGMODES
InadditiontoRegularmodewhereinputandoutputstreamsareoperating
at the same rate, the IDT72V71623 incorporates a rate matching function,
Mux/Demux mode. In Mux/Demux mode, all input streams are operating at
the same rate, while output streams are operating at a different rate. All
configurationsarenon-blocking. Thesemodescanbeenteredbysettingthe
DR3-0 bits in the Control Register, see Table 5.
OUTPUTIMPEDANCECONTROL
Inordertoputallstreamsinthree-state,allper-channelthree-statecontrol
bitsintheConnectionMemoryareset(MOD0andMOD1=1)orboththeODE
pin and the OSB bit of the Control Register must be zero. If any combination
otherthan0-0,fortheODEpinandtheOSBbit,isused,thethree-statecontrol
ofthestreamswillbelefttothestateoftheMOD1andMOD0bitsoftheConnection
Memory. The IDT72V71623 incorporates a memory block programming
featuretofacilitatethree-statecontrolafterreset.SeeTable1forOutputHigh-
ImpedanceControl.
SERIAL DATA INTERFACE TIMING
When a 16Mb/s serial data rate is required, the master clock frequency
will be running at 16.384MHz resulting in a single-bit per clock. For all other
cases,2Mb/s,4Mb/s,and8Mb/s,themasterclockfrequencywillbetwicethe
fastestdatarateontheserialstreams.UseTable5todetermineclockspeed
andDR3-0bitsintheControlRegistertosetupthedevice.TheIDT72V71623
provides two different interface timing modes, ST-BUS or GCI. The
IDT72V71623automaticallydetectsthepresenceofaninputframepulseand
identifies it as either ST-BUS or GCI.
In ST-BUS, when running at 16.384MHz, data is clocked out on the
falling edge and is clocked in on the subsquent rising-edge. At all other data
rates, there are two clock cycles per bit and every second falling edge of the
masterclockmarksabitboundaryandthedataisclockedinontherisingedge
of CLK, three quarters of the way into the bit cell. See Figure 15 for timing.
In GCI format, when running at 16.384MHz, data is clocked out on the
rising edge and is clocked in on the subsquent falling edge. At all other data
rates, there are two clock cycles per bit and every second rising edge of the
masterclockmarksthebitboundaryanddataisclockedinonthefallingedge
of CLK at three quarters of the way into the bit cell. See Figure 16 for timing.
INPUT FRAME OFFSET SELECTION
Inputframeoffsetselectionallowsthechannelalignmentofindividualinput
streamstobeoffsetwithrespecttotheoutputstreamchannelalignment(i.e.F0i).
Although input data is synchronous, delays can be caused by variable path
serialbackplanesandvariablepathlengths,whichmaybeimplementedinlarge
centralizedanddistributedswitchingsystems.Becausedataisoftendelayed
thisfeatureisusefulincompensatingfortheskewbetweenclocks.
Eachinputstreamcanhaveitsowndelayoffsetvaluebyprogrammingthe
frameinputoffsetregisters(FOR,Table7).Theframeoffsetshownisafunction
ofthedatarate,andcanbeaslargeas+4.5masterclock(CLK)periodsforward
witharesolutionofclockperiod.Todeterminethemaximumoffsetallowed
see Table 8.
SERIAL INPUT FRAME ALIGNMENT EVALUATION
TheIDT72V71623providestheframeevaluation(FE)inputtodetermine
differentdatainputdelayswithrespecttotheframepulseF0i.Settingthestart
frameevaluation(SFE)bitlowforatleastoneframestartsameasurementcycle.
When the SFE bit in the Control Register is changed from low to high, the
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