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参数资料
| 型号： | IDT72V73250BB |
| 厂商： | IDT, Integrated Device Technology Inc |
| 文件页数： | 6/8页 |
| 文件大小： | 0K |
| 描述： | IC DGTL SW 8192X8192 144-BGA |
| 标准包装： | 10 |
| 系列： | 72V |
| 类型： | 多路复用器 |
| 电路： | 1 x 16:16 |
| 独立电路： | 1 |
| 电压电源： | 单电源 |
| 电源电压： | 3 V ~ 3.6 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 144-BGA |
| 供应商设备封装： | 144-PBGA（13x13） |
| 包装： | 托盘 |
| 其它名称： | 72V73250BB |
6
INDUSTRIAL TEMPERATURERANGE
IDT72V73250 3.3V TIME SLOT INTERCHANGE
DIGITAL SWITCH 8,192 x 8,192
bit of the Control Register is set to HIGH, the Block Programming Data will be
loaded into the bits 14 and 15 of every Connection Memory location. The other
ConnectionMemorybits(bit0tobit13)areloadedwithzeros.Whenthememory
block programming is complete, the device resets the Block Programming
Enable,BlockProgrammingData1-0 andMemoryBlockProgrambitstozero.
DELAY THROUGH THE IDT72V73250
Theswitchingofinformationfromtheinputserialstreamstotheoutputserial
streams results in a throughput delay. The device can be programmed to
performtime-slotinterchangefunctionswithdifferentthroughputdelaycapabili-
ties on a per-channel basis. For voice applications, variable throughput delay
isbestasitensureminimumdelaybetweeninputandoutputdata.Inwideband
dataapplications,constantthroughputdelayisbestastheframeintegrityofthe
information is maintained through the switch.
Thedelaythroughthedevicevariesaccordingtothetypeofthroughputdelay
selected in the MOD bits of the Connection Memory.
VARIABLE DELAY MODE (MOD1-0 = 0-0)
In this mode, the delay is dependent only on the combination of source and
destination channels and is independent of input and output streams. The
minimum delay achievable in the IDT72V73250 is three time-slots. If the input
channeldataisswitchedtothesameoutputchannel(channeln,framep),itwill
be output in the following frame (channel n, frame p+1). The same is true if the
input channel n is switched to output channel n+1 or n+2. If the input channel
n is switched to output channel n+3, n+4,..., the new output data will appear in
the same frame. Table 2 shows the possible delays for the IDT72V73250 in
Variable Delay mode.
CONSTANT DELAY MODE (MOD1-0 = 0-1)
In this mode, frame integrity is maintained in all switching configurations by
making use of a multiple data memory buffer. Input channel data is written into
the data memory buffers during frame n will be read out during frame n+2. In
theIDT72V73250,theminimumthroughputdelayachievableinConstantDelay
mode will be one frame plus one channel. See Table 1.
MICROPROCESSOR INTERFACE
The IDT72V73250’s microprocessor interface looks like a standard RAM
interface to improve integration into a system. With a 15-bit address bus and a
16-bitdatabus,readsandwritesaremappeddirectlyintoDataandConnection
memories. By allowing the internal memories to be randomly accessed, the
controlling microprocessor has more time to manage other peripheral devices
andcanmoreeasilyandquicklygatherinformationandsetuptheswitchpaths.
Table 4 shows the mapping of the addresses into internal memory blocks.
MEMORY MAPPING
Theaddressbusonthemicroprocessorinterfaceselectstheinternalregisters
and memories of the IDT72V73250.
Thetwomostsignificantbitsoftheaddressselectbetweentheregisters,Data
Memory,andConnectionMemory.IfA14andA13areHIGH,A12-A0areused
to address the Data Memory. If A14 is HIGH and A13 is LOW, A12-A0 are used
to address Connection Memory. If A14 is LOW and A13 is HIGH A12-A0 are
usedtoselecttheControlRegister,FrameAlignmentRegister,andFrameOffset
Registers. See Table 4 for mappings.
AsexplainedintheInitializationsections,aftersystempower-up,theControl
Registershouldbeprogrammedimmediatelytoestablishthedesiredswitching
configuration.
ThedataintheControlRegisterconsistsoftheMemoryBlockProgramming
bit,theBlockProgrammingDatabits,theBeginBlockProgrammingEnable,the
Output Stand By , Start Frame Evaluation, Output Enable Indication, and
Software Reset . As explained in the Memory Block Programming section, the
Block Programming Enable begins the programming if the Memory Block
Program bit is enabled. This allows the entire Connection Memory block to be
programmedwiththeBlockProgrammingDatabits.IftheODEpinisLOW,the
OutputStandBybitenables(ifHIGH)ordisables(ifLOW)allTXoutputdrivers.
If the ODE pin is HIGH, the contents of the Output Stand By bit is ignored and
all TX output drivers are enabled.
SOFTWARE RESET
The Software Reset serves the same function as the hardware reset. As with
the hard reset, the Software Reset must also be set HIGH for 20ns before
bringingtheSoftwareResetLOWagainfornormaloperation. OncetheSoftware
Reset is LOW, internal registers and other memories may be read or written.
During Software Reset, the microprocessor port is still able to read from all
internal memories. The only write operation allowed during a Software Reset
istotheSoftwareResetbitintheControlRegistertocompletetheSoftwareReset.
CONNECTION MEMORY CONTROL
If the ODE pin and the Output Stand By bit are LOW, all output channels will
be in three-state. See Table 3 for detail.
If MOD1-0 of the Connection Memory is 1-0 accordingly, the output channel
will be in Processor Mode. In this case the lower eight bits of the Connection
Memory are output each frame until the MOD1-0 bits are changed. If MOD1-
0oftheConnectionMemoryare0-1accordingly,thechannelwillbeinConstant
Delay Mode and bits 12-0 are used to address a location in Data Memory. If
MOD1-0 of the Connection Memory are 0-0, the channel will be in Variable
Delay Mode and bits 12-0 are used to address a location in Data Memory. If
MOD 1-0 of the Connection Memory are 1-1, the channel will be in High-
Impedance mode and that channel will be in three-state.
OUTPUT ENABLE INDICATION
TheIDT72V73250hasthecapabilitytoindicatethestateoftheoutputs(active
orthree-state)byenablingtheOutputEnableIndicationintheControlRegister.
In the Output Enable Indication mode however, only half of the output streams
are available. If this same capability is desired with all 16 streams, this can be
accomplished by using two IDT72V73250 or one IDT72V73260 devices. In
onedevice,theAllOutputEnablebitissettoaonewhileintheothertheAllOutput
Enable is set to zero. In this way, one device acts as the switch and the other
as a three-state control device, see Figure 5. It is important to note if the TSI
device is programmed for All Output Enable and the Output Enable Indication
is also set, the device will be in the All Output Enable mode not Output Enable
Indication. To use all 16 streams, set Output Enable Indication in the Control
Register to zero.
INITIALIZATION OF THE IDT72V73250
After power up, the state of the Connection Memory is unknown. As such,
theoutputsshouldbeputinhigh-impedancebyholdingtheODEpinLOW. While
theODEisLOW,themicroprocessorcaninitializethedevicebyusingtheBlock
Programmingfeatureandprogramtheactivepathsviathemicroprocessorbus.
Once the device is configured, the ODE pin (or Output Stand By bit depending
on initialization) can be switched to enable the TSI switch.
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