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| 型号： | IDT74ALVC74PY8 |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | 锁存器 |
| 英文描述： | ALVC/VCX/A SERIES, DUAL POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO14 |
| 封装： | SSOP-14 |
| 文件页数： | 1/6页 |
| 文件大小： | 72K |
| 代理商： | IDT74ALVC74PY8 |
INDUSTRIALTEMPERATURERANGE
IDT74ALVC74
3.3VCMOSDUALPOSITIVEEDGE-TRIGGEREDD-TYPEFLIP-FLOP
1
JUNE 2000
INDUSTRIAL TEMPERATURE RANGE
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
2000 Integrated Device Technology, Inc.
DSC-4639/1
FEATURES:
0.5 MICRON CMOS Technology
ESD > 2000V per MIL-STD-883, Method 3015; > 200V using
machine model (C = 200pF, R = 0)
VCC = 3.3V ± 0.3V, Normal Range
VCC = 2.7V to 3.6V, Extended Range
VCC = 2.5V ± 0.2V
CMOS power levels (0.4
W typ. static)
Rail-to-Rail output swing for increased noise margin
Available in SOIC, SSOP, and TSSOP packages
FUNCTIONAL BLOCK DIAGRAM
DRIVE FEATURES:
High Output Drivers: ±24mA
Suitable for Heavy Loads
APPLICATIONS:
3.3V high speed systems
3.3V and lower voltage computing systems
IDT74ALVC74
3.3V CMOS DUAL
POSITIVE EDGE-TRIGGERED
D-TYPE FLIP-FLOP WITH
CLEAR AND PRESET
DESCRIPTION:
T
his dual positive-edge-triggered D-type flip-flop is built using advanced
dual metal CMOS technology. A low level at the preset (PRE) or clear (CLR)
inputs sets or resets the outputs, regardless of the levels of the other inputs.
When PRE and CLR are inactive (high), data at the data (D) input meeting
thesetuptimerequirementsistransferredtotheoutputsonthepositive-going
edge of the clock pulse. Clock triggering occurs at a voltage level and is not
directly related to the rise time of the clock pulse. Following the hold-time
interval, data at the D input may be changed without affecting the levels at
the outputs.
The ALVC74 has been designed with a ±24mA output driver. This driver
is capable of driving a moderate to heavy load while maintaining speed
performance.
TG
C
PRE
CLK
C
TG
C
D
TG
C
TG
C
CLR
Q
相关PDF资料 |
PDF描述 |
|---|---|
| IDT74ALVC74PY | ALVC/VCX/A SERIES, DUAL POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO14 |
| IDT74ALVCF162835APV8 | ALVC/VCX/A SERIES, 18-BIT DRIVER, TRUE OUTPUT, PDSO56 |
| IDT74ALVCF162835APV | ALVC/VCX/A SERIES, 18-BIT DRIVER, TRUE OUTPUT, PDSO56 |
| IDT74ALVCH162245PAG8 | ALVC/VCX/A SERIES, DUAL 8-BIT TRANSCEIVER, TRUE OUTPUT, PDSO48 |
| IDT74ALVCH162245PV8 | ALVC/VCX/A SERIES, DUAL 8-BIT TRANSCEIVER, TRUE OUTPUT, PDSO48 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| IDT74ALVCF162835APA | 功能描述:IC UNIV BUS DVR 18BIT 56TSSOP RoHS:否 类别:集成电路 (IC) >> 逻辑 - 通用总线函数 系列:74ALVCF 产品变化通告:Product Discontinuation 09/Dec/2010 标准包装:1,500 系列:74AVC 逻辑类型:通用总线驱动器 输入数:- 电路数:18 位 输出电流高，低:12mA，12mA 电源电压:1.65 V ~ 3.6 V 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:56-TFSOP（0.240"，6.10mm 宽） 供应商设备封装:56-TSSOP 包装:带卷 (TR) |
| IDT74ALVCF162835APA8 | 功能描述:IC UNIV BUS DVR 18BIT 56TSSOP RoHS:否 类别:集成电路 (IC) >> 逻辑 - 通用总线函数 系列:74ALVCF 产品变化通告:Product Discontinuation 09/Dec/2010 标准包装:1,500 系列:74AVC 逻辑类型:通用总线驱动器 输入数:- 电路数:18 位 输出电流高，低:12mA，12mA 电源电压:1.65 V ~ 3.6 V 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:56-TFSOP（0.240"，6.10mm 宽） 供应商设备封装:56-TSSOP 包装:带卷 (TR) |
| IDT74ALVCF162835APAG | 功能描述:IC UNIV BUS DVR 18BIT 56TSSOP RoHS:是 类别:集成电路 (IC) >> 逻辑 - 通用总线函数 系列:74ALVCF 产品变化通告:Product Discontinuation 09/Dec/2010 标准包装:1,500 系列:74AVC 逻辑类型:通用总线驱动器 输入数:- 电路数:18 位 输出电流高，低:12mA，12mA 电源电压:1.65 V ~ 3.6 V 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:56-TFSOP（0.240"，6.10mm 宽） 供应商设备封装:56-TSSOP 包装:带卷 (TR) |
| IDT74ALVCF162835APAG8 | 功能描述:IC UNIV BUS DVR 18BIT 56TSSOP RoHS:是 类别:集成电路 (IC) >> 逻辑 - 通用总线函数 系列:74ALVCF 产品变化通告:Product Discontinuation 09/Dec/2010 标准包装:1,500 系列:74AVC 逻辑类型:通用总线驱动器 输入数:- 电路数:18 位 输出电流高，低:12mA，12mA 电源电压:1.65 V ~ 3.6 V 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:56-TFSOP（0.240"，6.10mm 宽） 供应商设备封装:56-TSSOP 包装:带卷 (TR) |
| IDT74ALVCF162835APF | 功能描述:IC UNIV BUS DVR 18BIT 56TVSOP RoHS:否 类别:集成电路 (IC) >> 逻辑 - 通用总线函数 系列:74ALVCF 产品变化通告:Product Discontinuation 09/Dec/2010 标准包装:1,500 系列:74AVC 逻辑类型:通用总线驱动器 输入数:- 电路数:18 位 输出电流高，低:12mA，12mA 电源电压:1.65 V ~ 3.6 V 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:56-TFSOP（0.240"，6.10mm 宽） 供应商设备封装:56-TSSOP 包装:带卷 (TR) |
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