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| 型号： | IDT74ALVCH16823PF8 |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | 总线收发器 |
| 英文描述： | ALVC/VCX/A SERIES, DUAL 9-BIT DRIVER, TRUE OUTPUT, PDSO56 |
| 封装： | 0.40 MM PITCH, TVSOP-56 |
| 文件页数： | 1/7页 |
| 文件大小： | 69K |
| 代理商： | IDT74ALVCH16823PF8 |
INDUSTRIALTEMPERATURERANGE
IDT74ALVCH16823
3.3VCMOS18-BITBUS-INTERFACEFLIP-FLOPWITH3-STATEOUTPUTS
1
APRIL 1999
INDUSTRIAL TEMPERATURE RANGE
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
1999 Integrated Device Technology, Inc.
DSC-4237/1
FEATURES:
0.5 MICRON CMOS Technology
Typical tSK(o) (Output Skew) < 250ps
ESD > 2000V per MIL-STD-883, Method 3015; > 200V using
machine model (C = 200pF, R = 0)
VCC = 3.3V ± 0.3V, Normal Range
VCC = 2.7V to 3.6V, Extended Range
VCC = 2.5V ± 0.2V
CMOS power levels (0.4
W typ. static)
Rail-to-Rail output swing for increased noise margin
Available in SSOP, TSSOP, and TVSOP packages
FUNCTIONAL BLOCK DIAGRAM
DRIVE FEATURES:
High Output Drivers: ±24mA
Suitable for heavy loads
APPLICATIONS:
3.3V high speed systems
3.3V and lower voltage computing systems
IDT74ALVCH16823
3.3V CMOS 18-BIT
BUS-INTERFACE FLIP-
FLOP WITH 3-STATE OUT-
PUTS AND BUS-HOLD
DESCRIPTION:
This18-bitbus-interfaceflip-flopisbuiltusingadvanceddualmetalCMOS
technology.TheALVCH16823features3-stateoutputsdesignedspecifically
for driving highly capacitive or relatively low-impedance loads. The device is
particularlysuitableforimplementingwiderbufferregisters,I/Oports,bidirec-
tional bus drivers with parity, and working registers.
TheALVCH16823canbeusedastwo9-bitflip-flopsorone18-bitflip-flop.
Withtheclock-enable(CLKEN)inputlow,theD-typeflip-flopsenterdataonthe
low-to-hightransitionsoftheclock.TakingCLKENhighdisablestheclockbuffer,
thuslatchingtheoutputs.Takingtheclear(CLR)inputlowcausestheQoutputs
to go low independently of the clock.
A buffered output-enable (OE)input can beused to placethenineoutputs
ineitheranormallogicstate(highorlowlogiclevels)orahigh-impedancestate.
In the high-impedance state, the outputs neither load nor drive the bus lines
significantly. The high-impedance state and increased drive provide the
capabilitytodrivebuslineswithoutneedforinterfaceorpullupcomponents.The
OEinputdoesnotaffecttheinternaloperationoftheflip-flops.Olddatacanbe
retainedornewdatacanbeenteredwhiletheoutputsareinthehigh-impedance
state.
The ALVCH16823 has been designed with a ±24mA output driver. This
driveriscapableofdrivingamoderatetoheavyloadwhilemaintainingspeed
performance.
The ALVCH16823 has “bus-hold” which retains the inputs’ last state
whenevertheinputgoestoahighimpedance. Thispreventsfloatinginputsand
eliminatestheneedforpull-up/downresistor.
TO 8 OTHER CHANNELS
1
OE
2
56
55
1
CE
R
C 1
3
1
Q1
D1
1
CLR
1
CLKEN
1
CLK
1
D1
54
TO 8 OTHER CHANNELS
2
OE
27
29
30
28
CE
R
C 1
15
2
Q1
D1
2
CLR
2
CLKE N
2
CLK
2
D 1
42
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