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| 型号： | IDT74ALVCHR16409PF |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | 总线收发器 |
| 英文描述： | ALVC/VCX/A SERIES, 18-BIT EXCHANGER, TRUE OUTPUT, PDSO56 |
| 封装： | TVSOP-56 |
| 文件页数： | 1/8页 |
| 文件大小： | 84K |
| 代理商： | IDT74ALVCHR16409PF |
1
EXTENDED COMMERCIAL TEMPERATURE RANGE
IDT74ALVCHR16409
3.3V CMOS 9-BIT, 4-PORT UNIVERSAL BUS EXCHANGER
CLK
D
1
A1
2
A1
CLK
D
1
Ax
2
Ax
1
Ax
1
Bx
2
Bx
3
2
Ax
1
Bx
2
Bx
3
CLK
SELEN
56
55
SEL0
SEL1
2
27
Flow and Storage Control
SEL3
SEL4
SEL2
PRE
1
28
29
30
CLK
D
CLK
D
1
Ax
2
Ax
2
Bx
1
Ax
2
Ax
1
Bx
3
1
Bx
2
Bx
1
B1
2
B1
One of 9 Channels
3
15
54
42
NO
T RECOMMENDED
FOR
NEW
DESIGNS
FOR
NEW
DESIGNS
FOR
NEW
DESIGNS
FOR
NEW
DESIGNS
FOR
NEW
DESIGNS
OCTOBER 1999
1999 Integrated Device Technology, Inc.
DSC-4586/-
c
IDT74ALVCHR16409
EXTENDED COMMERCIAL TEMPERATURE RANGE
3.3V CMOS 9-BIT, 4-PORT
UNIVERSAL BUS EXCHANGER
WITH 3-STATE OUTPUTS
AND BUS-HOLD
APPLICATIONS:
DESCRIPTION:
3.3V High Speed Systems
3.3V and lower voltage computing systems
FEATURES:
– 0.5 MICRON CMOS Technology
–Typical tSK(0) (Output Skew) < 250ps
– ESD > 2000V per MIL-STD-883, Method 3015;
> 200V using machine model (C = 200pF, R = 0)
– 0.635mm pitch SSOP, 0.50mm pitch TSSOP,
and 0.40mm pitch TVSOP packages
– Extended commercial range of – 40°C to + 85°C
–VCC = 3.3V ± 0.3V, Normal Range
–VCC = 2.7V to 3.6V, Extended Range
–VCC = 2.5V ± 0.2V
– CMOS power levels (0.4W typ. static)
– Rail-to-Rail output swing for increased noise margin
This 9-bit, 4-port universal bus exchanger is built using advanced
dual metal CMOS technology. The ALVCHR16409 allows synchronous
data exchange between four different buses. Data flow is controlled by
the select (SEL0–SEL4) inputs. A data-flow state is stored on the rising
edge of the clock (CLK) input if the select-enable (SELEN) input is low.
Once a data-flow state has been established, data is stored in the flip-flop
on the rising edge of CLK if SELEN is high. The data-flow control logic is
designed to allow glitch-free data transmission.
When preset (PRE) transitions high, the outputs are disabled imme-
diately without waiting for a clock pulse. To leave the high-impedance
state, both PRE and SELEN must be low and a clock pulse must be
applied.
The ALVCHR16409 has been designed with a ±24mA output driver.
This driver is capable of driving a moderate to heavy load while
maintaining speed performance.
The ALVCHR16409 has “bus-hold” which retains the inputs’ last state
whenever the input bus goes to a high impedance. This prevents floating
inputs and eliminates the need for pull-up/down resistors.
FUNCTIONAL BLOCK DIAGRAM
Drive Features for ALVCHR16409:
– Balanced Output Drivers: ±12mA
– Low switching noise
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