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参数资料
| 型号： | IDT74FCT162841BTEG |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | 总线收发器 |
| 英文描述： | FCT SERIES, DUAL 10-BIT DRIVER, TRUE OUTPUT, CDFP56 |
| 封装： | 0.635 MM PITCH, CERPACK-56 |
| 文件页数： | 7/8页 |
| 文件大小： | 118K |
| 代理商： | IDT74FCT162841BTEG |
7
IDT54/74FCT162841AT/BT/CT/ET
FAST CMOS 20-BIT TRANSPARENT LATCH
MILITARYANDCOMMERCIALTEMPERATURERANGES
Pulse
Generator
R T
D.U.T.
V CC
V IN
C L
V OUT
50pF
500
500
7.0V
3V
1.5V
0V
3V
1.5V
0V
3V
1.5V
0V
3V
1.5V
0V
DATA
INPUT
TIMING
INPUT
ASYNCHRONO US CONTROL
PRES ET
CLEAR
ETC.
SYNCHRO NOUS CO NT ROL
tSU
tH
tRE M
tSU
tH
PRES ET
CLEAR
CLOCK ENABLE
ETC.
HIGH-LOW -HIGH
PULS E
LO W -HIGH-LOW
PULS E
tW
1.5V
SAM E PHASE
INPUT TRANSITIO N
3V
1.5V
0V
1.5V
VOH
tPLH
OUTPUT
OPPO SITE P HASE
INPUT TRANSITIO N
3V
1.5V
0V
tPLH
tPH L
VOL
CONTRO L
INPUT
3V
1.5V
0V
3.5V
0V
OUTPUT
NORMA LLY
LO W
OUTPUT
NORMA LLY
HIG H
SW ITCH
CLOSE D
SW ITCH
OPEN
VOL
0.3V
tPLZ
tPZL
tPZH
tPHZ
3.5V
0V
1.5V
ENAB LE
DISA BLE
VOH
TEST CIRCUITS AND WAVEFORMS
PROPAGATION DELAY
TEST CIRCUITS FOR ALL OUTPUTS
ENABLE AND DISABLE TIMES
SET-UP, HOLD, AND RELEASE TIMES
PULSE WIDTH
SWITCH POSITION
Test
Switch
Open Drain
Disable Low
Closed
Enable Low
All Other Tests
Open
5v16-link
DEFINITIONS:
CL = Load capacitance: includes jig and probe capacitance.
RT = Termination resistance: should be equal to ZOUT of the Pulse
Generator.
NOTES:
1. Diagram shown for input Control Enable-LOW and input Control
Disable-HIGH.
2. Pulse Generator for All Pulses: Rate
≤ 1.0MHz; tF ≤ 2.5ns; tR ≤ 2.5ns.
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