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参数资料
| 型号： | IDT74FCT162952ETE |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | 总线收发器 |
| 英文描述： | FCT SERIES, DUAL 8-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, CDFP56 |
| 封装： | 0.635 MM PITCH, CERPACK-56 |
| 文件页数： | 6/7页 |
| 文件大小： | 124K |
| 代理商： | IDT74FCT162952ETE |
6
MILITARYANDCOMMERCIALTEMPERATURERANGES
IDT54/74FCT162952AT/BT/CT/ET
FASTCMOS16-BITREGISTEREDTRANSCEIVER
Pulse
Generator
R T
D.U.T.
V CC
VIN
C L
V OUT
50pF
500
500
7.0V
3V
1.5V
0V
3V
1.5V
0V
3V
1.5V
0V
3V
1.5V
0V
DATA
INPUT
TIMING
INPUT
ASYNCHR ONOUS C ONTROL
PRESET
CLEAR
ETC.
SYNCHRONOUS CONT ROL
tSU
tH
tREM
tSU
tH
PRESET
CLEAR
CLOCK ENABLE
ETC.
HIGH-LOW -HIGH
PULSE
LOW -HIGH-LOW
PULSE
tW
1.5V
SAM E PHASE
INPUT TRANSITION
3V
1.5V
0V
1.5V
VOH
tPLH
OUTPUT
OPPOSITE PHASE
INPUT TRANSITION
3V
1.5V
0V
tPLH
tPHL
VOL
CONTROL
INPUT
3V
1.5V
0V
3.5V
0V
OUTPUT
NORMALLY
LOW
OUTPUT
NORMALLY
HIGH
SW ITCH
CLOSED
SW ITCH
OPEN
VOL
0.3V
tPLZ
tPZL
tPZH
tPHZ
3.5V
0V
1.5V
ENABLE
DISABLE
VOH
TEST CIRCUITS AND WAVEFORMS
PROPAGATION DELAY
TEST CIRCUITS FOR ALL OUTPUTS
ENABLE AND DISABLE TIMES
SET-UP, HOLD, AND RELEASE TIMES
PULSE WIDTH
SWITCH POSITION
Test
Switch
Open Drain
Disable Low
Closed
Enable Low
All Other Tests
Open
5v16-link
DEFINITIONS:
CL = Load capacitance: includes jig and probe capacitance.
RT = Termination resistance: should be equal to ZOUT of the Pulse
Generator.
NOTES:
1. Diagram shown for input Control Enable-LOW and input Control
Disable-HIGH.
2. Pulse Generator for All Pulses: Rate
≤ 1.0MHz; tF ≤ 2.5ns; tR ≤ 2.5ns.
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