参数资料
型号: IDT74FCT164245TPAG8
厂商: IDT, Integrated Device Technology Inc
文件页数: 1/8页
文件大小: 0K
描述: TRANSLATOR 16BIT BIDIR 48-TSSOP
标准包装: 1
系列: 74FCT
逻辑功能: 变换器,双向,3 态
位数: 16
输入类型: 电压
输出类型: 电压
通道数: 2
输出/通道数目: 8
差分 - 输入:输出: 无/无
传输延迟(最大): 5ns
电源电压: 2.7 V ~ 3.6 V
工作温度: -40°C ~ 85°C
封装/外壳: 48-TFSOP(0.240",6.10mm 宽)
供应商设备封装: 48-TSSOP
包装: 标准包装
产品目录页面: 1258 (CN2011-ZH PDF)
其它名称: 800-1859-6
1
IDT74FCT164245T
FAST CMOS 16-BIT BIDIRECTIONAL 3.3V TO 5V TRANSLATOR
INDUSTRIALTEMPERATURERANGE
SEPTEMBER 2009
INDUSTRIAL TEMPERATURE RANGE
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
2009 Integrated Device Technology, Inc.
DSC-2555/9
FEATURES:
0.5 MICRON CMOS Technology
Bidirectional interface between 3.3V and 5V buses
Control inputs can be driven from either 3.3V or 5V circuits
ESD > 2000V per MIL-STD-883, Method 3015; > 200V using
machine model (C = 200pF, R = 0)
VCC1 = 5V ±10%, VCC2 = 2.7V to 3.6V
High drive outputs (-32mA IOH, 64mA IOL) on 5V port
Power off disable on both ports permits “live insertion”
Typical VOLP (Output Ground Bounce) < 0.9V at VCC1 = 5V,
VCC2 = 3.3V, TA = 25°C
Available in SSOP and TSSOP packages
FUNCTIONAL BLOCK DIAGRAM
IDT74FCT164245T
FAST CMOS 16-BIT
BIDIRECTIONAL
3.3V TO 5V TRANSLATOR
DESCRIPTION:
The FCT164245T 16-bit 3.3V-to-5V translator is built using advanced
dual metal CMOS technology. This high-speed, low-power transceiver is
designed to interface between a 3.3V bus and a 5V bus in a mixed 3.3V/
5V supply environment. This enables system designers to interface TTL
compatible 3.3V components with 5V components. The direction and output
enable controls operate these devices as either two independent 8-bit
transceivers or one 16-bit transceiver. The A port interfaces with the 3.3V
bus; the B port interfaces with the 5V bus. The direction control (xDIR) pin
controls the direction of data flow. The output enable pin (x
OE) overrides
the direction control and disables both ports. These control signals can be
driven from either 3.3V or 5V devices.
The FCT164245T is ideally suited for driving high-capacitance loads
and low-impedance backplanes. The output buffers are designed with
power off disable capability to allow "hot insertion" of boards when used as
backplane drivers. They also allow interface between a mixed supply
system and external 5 volt peripherals.
1
DIR
1
OE
1
A1
1
A2
1
A3
1
A4
1
A5
1
A6
1
A7
1
A8
1
B1
1
B2
1
B3
1
B4
1
B5
1
B6
1
B7
1
B8
3.3V
Port
5V
Port
2
DIR
2
OE
2
A1
2
A2
2
A3
2
A4
2
A5
2
A6
2
A7
2
A8
2
B1
2
B2
2
B3
2
B4
2
B5
2
B6
2
B7
2
B8
3.3V
Port
5V
Port
1
47
48
2
3
5
6
46
44
43
41
40
38
37
8
9
11
12
24
36
35
33
32
30
25
29
27
26
22
23
13
14
16
17
19
20
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