- 您现在的位置：买卖IC网 > PDF目录65590 > IDT74LVC02ADC8 (INTEGRATED DEVICE TECHNOLOGY INC) LVC/LCX/Z SERIES, QUAD 2-INPUT NOR GATE, PDSO14 PDF资料下载
参数资料
| 型号： | IDT74LVC02ADC8 |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | 门电路 |
| 英文描述： | LVC/LCX/Z SERIES, QUAD 2-INPUT NOR GATE, PDSO14 |
| 封装： | 1.27 MM PITCH, SOIC-14 |
| 文件页数： | 4/5页 |
| 文件大小： | 94K |
| 代理商： | IDT74LVC02ADC8 |
4
EXTENDEDCOMMERCIALTEMPERATURERANGE
IDT74LVC02A
3.3V CMOS QUADRUPLE 2-INPUT POSITIVE-NOR GATE
O pen
V LOAD
GN D
VCC
Pulse
G enerator
D.U.T.
500
500
C L
R T
VIN
VOUT
(1, 2)
LVC Q U A D Link
IN PU T
VIH
0V
VOH
V OL
tPLH1
tSK (x)
OU TP U T 1
OU TP U T 2
tPHL1
tSK (x)
tPLH2
tPHL2
VT
V OH
VT
VOL
tSK(x) = tPLH2 - tPLH1 or tPHL2 - tPHL1
LV C QUAD L in k
DA TA
IN PU T
0V
tREM
TIM IN G
IN PU T
AS YN C H RO N O U S
CO NTRO L
SY NCH RO NO US
CO NTRO L
tSU
tH
tSU
tH
V IH
VT
V IH
VT
V IH
VT
V IH
VT
LO W -H IGH -LOW
PU LSE
H IG H -LO W -H IG H
PU LSE
VT
tW
SA M E PH AS E
IN PU T TR AN S ITIO N
O PPO SITE P H AS E
IN PU T TR AN S ITIO N
0V
VOH
VOL
tPLH
tPHL
tPLH
OU TPU T
VT
VIH
VT
VIH
VT
CO NTRO L
IN PU T
tPLZ
0V
OU TPU T
NO RM ALLY
LO W
tPZH
0V
SW ITCH
CL O SE D
OU TPU T
NO RM ALLY
HIG H
EN ABLE
D ISAB LE
SW ITCH
OP EN
tPHZ
0V
VLZ
V OH
VT
tPZL
VLOAD/2
VIH
VT
VOL
V HZ
LV C QUAD L in k
LVC Q U AD Link
LVC QU AD L in k
TEST CIRCUITS AND WAVEFORMS
TEST CONDITIONS
PROPAGATION DELAY
TEST CIRCUITS FOR ALL OUTPUTS
ENABLE AND DISABLE TIMES
SET-UP, HOLD, AND RELEASE TIMES
SWITCH POSITION
OUTPUT SKEW - tsk (x)
PULSE WIDTH
Symbol
VCC(1)= 2.5V ±0.2V
VCC(2)= 3.3V ±0.3V & 2.7V
Unit
VLOAD
2 x Vcc
6
V
VIH
Vcc
2.7
V
VT
VCC / 2
1.5
V
VLZ
150
300
mV
VHZ
150
300
mV
CL
30
50
pF
LVC QUAD Link
NOTE:
1. Diagram shown for input Control Enable-LOW and input Control
Disable-HIGH.
NOTES:
1. For tSK(o) OUTPUT1 and OUTPUT2 are any two outputs.
2. For tSK(b) OUTPUT1 and OUTPUT2 are in the same bank.
Test
Switch
Open Drain
Disable Low
Enable Low
VLOAD
Disable High
Enable High
GND
All Other tests
Open
LVC QUAD Link
CL=
Load capacitance: includes jig and probe capacitance.
RT = Termination resistance: should be equal to ZOUT of the Pulse
Generator.
NOTES:
1. Pulse Generator for All Pulses: Rate
≤ 10MHz; tF ≤ 2ns; tR ≤ 2ns.
2. Pulse Generator for All Pulses: Rate
≤ 10MHz; tF ≤ 2.5ns; tR ≤ 2.5ns.
相关PDF资料 |
PDF描述 |
|---|---|
| IDT74LVC02ADCG8 | LVC/LCX/Z SERIES, QUAD 2-INPUT NOR GATE, PDSO14 |
| IDT74LVC02APY | LVC/LCX/Z SERIES, QUAD 2-INPUT NOR GATE, PDSO14 |
| IDT74LVC04APY8 | LVC/LCX/Z SERIES, HEX 1-INPUT INVERT GATE, PDSO14 |
| IDT74LVC06ADC | LVC/LCX/Z SERIES, HEX 1-INPUT INVERT GATE, PDSO14 |
| IDT74LVC109APG8 | LVC/LCX/Z SERIES, DUAL POSITIVE EDGE TRIGGERED J-KBAR FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO16 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| IDT74LVC112APY | 制造商:Integrated Device Technology Inc 功能描述:Flip Flop, Dual, J/K Type, 16 Pin, Plastic, SSOP |
| IDT74LVC138ADC | 制造商:Integrated Device Technology Inc 功能描述: |
| IDT74LVC162244APA | 制造商:Integrated Device Technology Inc 功能描述: |
| IDT74LVC162244APAG | 功能描述:IC BUFF DVR TRI-ST 16BIT 48TSSOP RoHS:是 类别:集成电路 (IC) >> 逻辑 - 缓冲器，驱动器，接收器，收发器 系列:74LVC 标准包装:2,000 系列:74LVCH 逻辑类型:缓冲器/线路驱动器，非反相 元件数:2 每个元件的位元数:4 输出电流高，低:24mA，24mA 电源电压:1.65 V ~ 3.6 V 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:20-SOIC（0.295"，7.50mm 宽） 供应商设备封装:20-SOIC 包装:带卷 (TR) |
| IDT74LVC162244APAG8 | 功能描述:IC BUFF DVR TRI-ST 16BIT 48TSSOP RoHS:是 类别:集成电路 (IC) >> 逻辑 - 缓冲器，驱动器，接收器，收发器 系列:74LVC 标准包装:47 系列:74LVX 逻辑类型:缓冲器/线路驱动器，非反相 元件数:4 每个元件的位元数:1 输出电流高，低:4mA，4mA 电源电压:2 V ~ 3.6 V 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:14-SOIC（0.209"，5.30mm 宽） 供应商设备封装:14-SOIC 包装:管件 |
发布紧急采购，3分钟左右您将得到回复。