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| 型号： | IDT74LVC138AQ8 |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | 编、解码器及复用、解复用 |
| 英文描述： | LVC/LCX/Z SERIES, OTHER DECODER/DRIVER, INVERTED OUTPUT, PDSO16 |
| 封装： | QSOP-16 |
| 文件页数： | 1/6页 |
| 文件大小： | 81K |
| 代理商： | IDT74LVC138AQ8 |
INDUSTRIALTEMPERATURERANGE
IDT74LVC138A
3.3VCMOS3-LINE TO 8-LINE DECODER/DEMULTIPLEXER
1
AUGUST 1999
INDUSTRIAL TEMPERATURE RANGE
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
1999 Integrated Device Technology, Inc.
DSC-4722/1
FEATURES:
0.5 MICRON CMOS Technology
ESD > 2000V per MIL-STD-883, Method 3015; > 200V using
machine model (C = 200pF, R = 0)
VCC = 3.3V ± 0.3V, Normal Range
VCC = 2.7V to 3.6V, Extended Range
CMOS power levels (0.4
W typ. static)
Rail-to-Rail output swing for increased noise margin
All inputs, outputs, and I/Os are 5V tolerant
Supports hot insertion
Available in QSOP, SOIC, SSOP, and TSSOP packages
FUNCTIONAL BLOCK DIAGRAM
DRIVE FEATURES:
High Output Drivers: ±24mA
Reduced system switching noise
APPLICATIONS:
5V and 3.3V mixed voltage systems
Data communication and telecommunication systems
IDT74LVC138A
DESCRIPTION:
The LVC138A 3-line to 8-line decoder/demultiplexer is built using
advanced dual metal CMOS technology. This device is designed for high-
performance memory-decoding or data-routing applications requiring very
short propagation delay times. In high performance memory systems, this
decoder minimizes the effects of system decoding. When employed with
high-speed memories utilizing a fast enable circuit, the delay times of these
decodersandtheenabletimeofthememoryareusuallylessthanthetypical
access time of the memory. This means that the effective system delay
introduced by the decoder is negligible.
The conditions at the binary-select inputs and the three enable inputs
selectoneofeightoutputlines.Twoactive-lowenableinputsandoneactive-
high enable input reduce the need for external gates or inverters when
expanding. A 24-line decoder can be implemented without external invert-
ers and a 32-line decoder requires only one inverter. An enable input can
be used as a data input for demultiplexing applications.
Inputs can be driven from either 3.3V or 5V devices. This feature allows
the use of this device as a translator in a mixed 3.3V/5V supply system.
The LVC138A has been designed with a ±24mA output driver. This
driver is capable of driving a moderate to heavy load while maintaining
speed performance.
3.3V CMOS
3-LINE TO 8-LINE
DECODER/DEMULTIPLEXER
WITH 5 VOLT TOLERANT I/O
Y0
15
G1
Y1
14
Y2
13
Y3
12
A
1
2
3
B
Select
Inputs
Data
Outputs
Enable
Inputs
G2A
G2B
6
4
5
C
Y4
11
Y5
10
Y6
9
Y7
7
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| IDT74LVC138AQ | LVC/LCX/Z SERIES, OTHER DECODER/DRIVER, INVERTED OUTPUT, PDSO16 |
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| IDT74LVC158APY8 | LVC/LCX/Z SERIES, QUAD 2 LINE TO 1 LINE MULTIPLEXER, INVERTED OUTPUT, PDSO16 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| IDT74LVC162244APA | 制造商:Integrated Device Technology Inc 功能描述: |
| IDT74LVC162244APAG | 功能描述:IC BUFF DVR TRI-ST 16BIT 48TSSOP RoHS:是 类别:集成电路 (IC) >> 逻辑 - 缓冲器，驱动器，接收器，收发器 系列:74LVC 标准包装:2,000 系列:74LVCH 逻辑类型:缓冲器/线路驱动器，非反相 元件数:2 每个元件的位元数:4 输出电流高，低:24mA，24mA 电源电压:1.65 V ~ 3.6 V 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:20-SOIC（0.295"，7.50mm 宽） 供应商设备封装:20-SOIC 包装:带卷 (TR) |
| IDT74LVC162244APAG8 | 功能描述:IC BUFF DVR TRI-ST 16BIT 48TSSOP RoHS:是 类别:集成电路 (IC) >> 逻辑 - 缓冲器，驱动器，接收器，收发器 系列:74LVC 标准包装:47 系列:74LVX 逻辑类型:缓冲器/线路驱动器，非反相 元件数:4 每个元件的位元数:1 输出电流高，低:4mA，4mA 电源电压:2 V ~ 3.6 V 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:14-SOIC（0.209"，5.30mm 宽） 供应商设备封装:14-SOIC 包装:管件 |
| IDT74LVC162244APFG | 功能描述:IC BUFF DVR TRI-ST 16BIT 48TVSOP RoHS:是 类别:集成电路 (IC) >> 逻辑 - 缓冲器，驱动器，接收器，收发器 系列:74LVC 标准包装:47 系列:74LVX 逻辑类型:缓冲器/线路驱动器，非反相 元件数:4 每个元件的位元数:1 输出电流高，低:4mA，4mA 电源电压:2 V ~ 3.6 V 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:14-SOIC（0.209"，5.30mm 宽） 供应商设备封装:14-SOIC 包装:管件 |
| IDT74LVC162244APFG8 | 功能描述:IC BUFF DVR TRI-ST 16BIT 48TVSOP RoHS:是 类别:集成电路 (IC) >> 逻辑 - 缓冲器，驱动器，接收器，收发器 系列:74LVC 标准包装:47 系列:74LVX 逻辑类型:缓冲器/线路驱动器，非反相 元件数:4 每个元件的位元数:1 输出电流高，低:4mA，4mA 电源电压:2 V ~ 3.6 V 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:14-SOIC（0.209"，5.30mm 宽） 供应商设备封装:14-SOIC 包装:管件 |
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