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| 型号： | IDT74LVC169ADC8 |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | 计数器 |
| 英文描述： | LVC/LCX/Z SERIES, SYN POSITIVE EDGE TRIGGERED 4-BIT BIDIRECTIONAL BINARY COUNTER, PDSO16 |
| 封装： | SOIC-16 |
| 文件页数： | 1/8页 |
| 文件大小： | 103K |
| 代理商： | IDT74LVC169ADC8 |
1
EXTENDEDCOMMERCIALTEMPERATURERANGE
IDT74LVC169A
3.3V CMOS PRESETTABLE SYNCHRONOUS 4-BIT UP/DOWN
0
12
3
4
5
6
7
8
9
10
11
12
13
14
15
CO UNT DOW N
COUNT UP
NO
T RECOMMENDED
FOR
NEW
DESIGNS
FOR
NEW
DESIGNS
FOR
NEW
DESIGNS
FOR
NEW
DESIGNS
FOR
NEW
DESIGNS
OCTOBER 1999
1999
Integrated Device Technology, Inc.
DSC-5159/-
c
IDT74LVC169A
EXTENDED COMMERCIAL TEMPERATURE RANGE
DESCRIPTION:
The LVC169A is a high-performance, low-power, low-voltage, Si-gate
CMOS device, superiortomost advanced CMOS-compatibleTTLfamilies.
FEATURES:
– 0.5 MICRON CMOS Technology
– ESD > 2000V per MIL-STD-883, Method 3015;
> 200V using machine model (C = 200pF, R = 0)
– 1.27mm pitch SOIC, 0.635mm pitch QSOP,
0.65mm pitch SSOP, 0.65mm pitch TSSOP packages
– Extended commercial range of – 40°C to +85°C
–VCC = 3.3V ±0.3V, Normal Range
–VCC = 2.3V to 3.6V, Extended Range
– CMOS power levels (0.4W typ. static)
– Rail-to-Rail output swing for increased noise margin
– All inputs, outputs and I/O are 5 Volt tolerant
– Supports hot insertion
3.3V CMOS PRESETTABLE
SYNCHRONOUS 4-BIT UP/DOWN
BINARY COUNTER
WITH 5 VOLT TOLERANT I/O
STATE DIAGRAM
Inputs can be driven from either 3.3V or 5V devices. This feature allows
the use of this device as a translator in a mixed 3.3V/5V supply system.
fmax =
tp(max) (CP to TC) + t
SU (CEP to CP)
1
Drive Features for LVC169A:
– High Output Drivers: ±24mA
– Reduced system switching noise
The LVC169A is a presettable synchronous binary counter which
features an internal look-ahead carry and can be used for high-speed
counting. Synchronous operation is provided by having all flip-flops clocked
simultaniously on the positive-going edge of the clock (CP). Outputs (Q
0 to
Q
3) of the counters may be preset to a high or low level. A low level at the
parallel enable input (PE) disables the counting action and causes the data
at inputs (D
0 to D3) to be loaded into the counter on the positive-going edge
of the clock (provided that the set-up and hold time requirements for PE are
met). Preset takes place regardless of the levels at the count enable inputs
(CEP and CET).
The look-ahead carry simplifies serial cascading of the counters. Both
count enable inputs (CEP and CET) must be high to count. The CET input
is fed forward to enable the terminal count output (TC). The TC output thus
enabled will produce a high output pulse of a duration approximately equal
to the next cascaded stage. The maximum clock frequency for the cascaded
counters is determined by the CP to TC propagation delay and CEP to CP
set-up time, according to the following formula:
APPLICATIONS:
5V and 3.3V mixed voltage systems
Data communication and telecommunication systems
相关PDF资料 |
PDF描述 |
|---|---|
| IDT74LVC169APY | LVC/LCX/Z SERIES, SYN POSITIVE EDGE TRIGGERED 4-BIT BIDIRECTIONAL BINARY COUNTER, PDSO16 |
| IDT74LVC169APG | LVC/LCX/Z SERIES, SYN POSITIVE EDGE TRIGGERED 4-BIT BIDIRECTIONAL BINARY COUNTER, PDSO16 |
| IDT74LVC137AQ8 | LVC/LCX/Z SERIES, OTHER DECODER/DRIVER, INVERTED OUTPUT, PDSO16 |
| IDT74LVC137ADC8 | LVC/LCX/Z SERIES, OTHER DECODER/DRIVER, INVERTED OUTPUT, PDSO16 |
| IDT74LVC137AQ | LVC/LCX/Z SERIES, OTHER DECODER/DRIVER, INVERTED OUTPUT, PDSO16 |
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| IDT74LVC169AXTPG | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Integrated Device Technology Inc 功能描述: |
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| IDT74LVC244APGG | 功能描述:IC BUFF/DVR TRI-ST DUAL 20TSSOP RoHS:是 类别:集成电路 (IC) >> 逻辑 - 缓冲器，驱动器，接收器，收发器 系列:74LVC 标准包装:1,000 系列:74ABT 逻辑类型:寄存收发器，非反相 元件数:1 每个元件的位元数:8 输出电流高，低:32mA，64mA 电源电压:4.5 V ~ 5.5 V 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:24-SOIC（0.295"，7.50mm 宽） 供应商设备封装:24-SOIC 包装:带卷 (TR) |
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