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参数资料
| 型号： | IDT74LVC1G126ADY8 |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | 总线收发器 |
| 英文描述： | LVC/LCX/Z SERIES, 1-BIT DRIVER, TRUE OUTPUT, PDSO5 |
| 封装： | 0.65 MM PITCH, PLASTIC, SOP-5 |
| 文件页数： | 1/6页 |
| 文件大小： | 104K |
| 代理商： | IDT74LVC1G126ADY8 |
1
EXTENDEDCOMMERCIALTEMPERATURERANGE
IDT74LVC1G126A
3.3V CMOS SINGLE BUS BUFFER GATE WITH 3-STATE OUTPUT
MAY 1999
1999
Integrated Device Technology, Inc.
DSC-4884/1
c
IDT74LVC1G126A
EXTENDED COMMERCIAL TEMPERATURE RANGE
DESCRIPTION:
This single bus buffer gate is built using advanced dual metal CMOS
technology. The LVC1G126A is designed for 1.65V to 3.6V VCC operation
and features independent line drivers with 3-state outputs. Each output is
disabled when the associated output-enable (OE) input is low.
To ensure the high-impedance state during power up or power down,
OE should be tied to GND through a pulldown resistor; the minimum value
of the resistor is determined by the current sourcing capability of the driver.
The LVC1G126A has been designed with a ±24mA output driver. This
driver is capable of driving a moderate to heavy load while maintaining
speed performance.
Inputs can be driven from either 3.3V or 5V devices. This feature allows
the use of this device as a translator in a mixed 3.3V/5V system environ-
ment.
PSOP
TOP VIEW
3.3V CMOS
SINGLE BUS BUFFER GATE
WITH 3-STATE OUTPUT
AND 5 VOLT TOLERANT I/O
A
OE
1
2
Y
4
GND
2
34
5
1
A
VCC
OE
Y
SO5-1
Functional Block Diagram
PIN CONFIGURATION
Drive Features for LVC1G126A:
–
High Output Drivers: ±24mA
–
Reduced system switching noise
FEATURES:
–
0.5 MICRON CMOS Technology
–
ESD > 2000V per MIL-STD-883, Method 3015;
> 200V using machine model (C = 200pF, R = 0)
–
0.65mm pitch PSOP package
–
Extended commercial range of – 40°C to +85°C
–VCC = 3.3V ±0.3V, Normal Range
–VCC = 1.65V to 3.6V, Extended Range
–VCC = 2.5V ±0.2V
–
CMOS power levels (0.4 W typ. static)
–
Rail-to-Rail output swing for increased noise margin
–
All inputs, outputs and I/O are 5 Volt tolerant
–
Supports hot insertion
APPLICATIONS:
5V and 3.3V mixed voltage systems
Data communication and telecommunication systems
PIN DESCRIPTION
Pin Names
Description
OE
Output Enable Input
A
Data Input
Y
3-State Output
FUNCTION TABLE(1)
Inputs
Output
OE
A
Y
HH
H
HL
L
LX
Z
NOTE:
1. H = HIGH Voltage Level
L = LOW Voltage Level
X = Don’t Care
Z = High-Impedance
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| IDT74LVC244APGG | 功能描述:IC BUFF/DVR TRI-ST DUAL 20TSSOP RoHS:是 类别:集成电路 (IC) >> 逻辑 - 缓冲器，驱动器，接收器，收发器 系列:74LVC 标准包装:1,000 系列:74ABT 逻辑类型:寄存收发器，非反相 元件数:1 每个元件的位元数:8 输出电流高，低:32mA，64mA 电源电压:4.5 V ~ 5.5 V 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:24-SOIC（0.295"，7.50mm 宽） 供应商设备封装:24-SOIC 包装:带卷 (TR) |
| IDT74LVC244APGG8 | 功能描述:IC BUFF/DVR TRI-ST DUAL 20TSSOP RoHS:是 类别:集成电路 (IC) >> 逻辑 - 缓冲器，驱动器，接收器，收发器 系列:74LVC 标准包装:1,000 系列:74ABT 逻辑类型:寄存收发器，非反相 元件数:1 每个元件的位元数:8 输出电流高，低:32mA，64mA 电源电压:4.5 V ~ 5.5 V 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:24-SOIC（0.295"，7.50mm 宽） 供应商设备封装:24-SOIC 包装:带卷 (TR) |
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