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参数资料
| 型号： | IDT74LVC652ASO8 |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | 总线收发器 |
| 英文描述： | LVC/LCX/Z SERIES, 8-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, PDSO24 |
| 封装： | 1.27 MM PITCH, SOIC-24 |
| 文件页数： | 4/7页 |
| 文件大小： | 93K |
| 代理商： | IDT74LVC652ASO8 |
INDUSTRIALTEMPERATURERANGE
4
IDT74LVC652A
3.3VCMOSOCTALBUSTRANSCEIVERANDREGISTER
Symbol
Parameter
Test Conditions
Min.
Typ.(1)
Max.
Unit
VIH
Input HIGH Voltage Level
VCC = 2.3V to 2.7V
1.7
—
V
VCC = 2.7V to 3.6V
2
—
VIL
Input LOW Voltage Level
VCC = 2.3V to 2.7V
—
0.7
V
VCC = 2.7V to 3.6V
—
0.8
IIH
Input Leakage Current
VCC = 3.6V
VI = 0 to 5.5V
—
±5A
IIL
IOZH
High Impedance Output Current
VCC = 3.6V
VO = 0 to 5.5V
—
±10
A
IOZL
(3-State Output pins)
IOFF
Input/Output Power Off Leakage
VCC = 0V, VIN or VO
≤ 5.5V
—
±50
A
VIK
Clamp Diode Voltage
VCC = 2.3V, IIN = –18mA
—
–0.7
–1.2
V
VH
Input Hysteresis
VCC = 3.3V
—
100
—
mV
ICCL
Quiescent Power Supply Current
VCC = 3.6V
VIN = GND or VCC
——
10
A
ICCH
ICCZ
3.6
≤ VIN ≤ 5.5V(2)
——
10
ICC
Quiescent Power Supply Current
One input at VCC - 0.6V, other inputs at VCC or GND
—
500
A
Variation
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
FollowingConditionsApplyUnlessOtherwiseSpecified:
Operating Condition: TA = –40°C to +85°C
NOTES:
1. Typical values are at VCC = 3.3V, +25°C ambient.
2. This applies in the disabled state only.
NOTES:
1. H = HIGH Voltage Level
X = Don’t Care
L = LOW Voltage Level
↑ = LOW-to-HIGH transition
2. Select Control = L: clocks can occur simultaneously.
Select Control = H: clocks can be staggered to load both registers.
3. The data output functions may be enabled or disabled by various signals at the OEAB or OEBA inputs. Data input functions are always enabled, i.e. data at the bus pins
will be stored on every LOW-to-HIGH transition of the clock inputs.
FUNCTION TABLE(1)
Inputs
Data I/O
(3)
OEAB
OEBA
CLKAB
CLKBA
SAB
SBA
Ax
Bx
Operation or Function
L
H
H or L
X
Input
Isolation
LH
↑↑
X
Store A and B data
XH
↑
H or L
X
Input
Unspecified(2)
Store A, Hold B
HH
↑↑
X(2)
X
Input
Output
Store A in both registers
L
X
H or L
↑
X
Unspecified(2)
Input
Store B, Hold A
LL
↑↑
XX(2)
Output
Input
Store B in both registers
L
X
L
Output
Input
Real time B data to A bus
L
X
H or L
X
H
Store B data to A bus
H
X
L
X
Input
Output
Real time A data to B bus
H
H or L
X
H
X
Store A data to B bus
H
L
H or L
H
Output
Store A data to B bus and
Store B data to A bus
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