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参数资料
| 型号： | IDT74LVCH16276APV8 |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | 总线收发器 |
| 英文描述： | LVC/LCX/Z SERIES, 12-BIT EXCHANGER, TRUE OUTPUT, PDSO56 |
| 封装： | SSOP-56 |
| 文件页数： | 3/8页 |
| 文件大小： | 72K |
| 代理商： | IDT74LVCH16276APV8 |
INDUSTRIALTEMPERATURERANGE
IDT74LVCH16276A
3.3VCMOS12-BITSYNCHRONOUSBUSEXCHANGER
3
Inputs
Outputs
Ax
CEA1B CEA2B
OEB
CLK
1Bx
2Bx
HLL
L
↑
HH
LL
L
↑
LL
HL
H
L
↑
HB(2)
LL
H
L
↑
LB(2)
HH
L
↑
B(2)
H
LH
L
↑
B(2)
L
XH
H
L
↑
B(2)
XX
X
H
↑
ZZ
XX
X
L
↑
Active
FUNCTION TABLES(1)
Inputs
Outputs
1Bx
2Bx
SEL
CE1B CE2B
OEA
CLK
Ax
HX
H
L
X
L
↑
H
LX
H
L
X
L
↑
L
XX
H
X
L
↑
A(2)
XH
L
X
L
↑
H
XL
L
X
L
↑
L
XX
L
X
H
L
↑
A(2)
X
XXX
H
↑
Z
NOTES:
1. H = HIGH Voltage Level
L = LOW Voltage Level
X = Don’t Care
Z = High-Impedance
↑ = LOW-to-HIGH Transition
2. A, B = Output level before the indicated steady-state input conditions were
established.
PIN DESCRIPTION
Signal
I/O
Description
A(1:12)
I/O
Bidirectional Data Port A. Usually connected to the CPU’s Address/Data bus.(1)
1B(1:12)
I/O
Bidirectional Data Port 1B. Usually connected to the even path or even bank of memory.(1)
2B(1:12)
I/O
Bidirectional Data Port 2B. Usually connected to the odd path or odd bank of memory.(1)
CLK
I
Clock Input.
CEA1B
I
Clock Enable Input for the A-1B Register. If CEA1B is LOW during the rising edge of CLK, data will be clocked into register A-1B (Active LOW).
CEA2B
I
Clock Enable Input for the A-2B Register. If CEA2B is LOW during the rising edge of CLK, data will be clocked into register A-2B (Active LOW).
CE1B
I
Clock Enable Input for the 1B-A Register. If CE1B is LOW during the rising edge of CLK, data will be clocked into register 1B-A (Active LOW).
CE2B
I
Clock Enable Input for the 2B-A Register. If CE2B is LOW during the rising edge of CLK, data will be clocked into register 2B-A (Active LOW).
SEL
I
1B or 2B Part Selection. When HIGH during the rising edge of CLK, SEL enables data transfer from 1B Port to A Port. When LOW during the rising
edge of CLK, SEL enables data transfer from 2B Port to A Port.
OEA
I
Synchronous Output Enable for A Port (Active LOW).
OEB
I
Synchronous Output Enable for 1B Port and 2B Port (Active LOW).
NOTE:
1. These pins have “Bus-hold”. All other pins are standard inputs, outputs, or I/Os.
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| IDT74LVCH16374APV | 制造商:Integrated Device Technology Inc 功能描述:74LVCH SMD 74LVCH16374 SSOP48 |
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