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参数资料
| 型号： | IDT74LVCH16952APF8 |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | 总线收发器 |
| 英文描述： | LVC/LCX/Z SERIES, DUAL 8-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, PDSO56 |
| 封装： | 0.40 MM PITCH, TVSOP-56 |
| 文件页数： | 2/6页 |
| 文件大小： | 75K |
| 代理商： | IDT74LVCH16952APF8 |
INDUSTRIALTEMPERATURERANGE
2
IDT74LVCH16952A
3.3V CMOS 16-BIT REGISTERED TRANSCEIVER
SSOP/ TSSOP/ TVSOP
TOP VIEW
PIN CONFIGURATION
Symbol
Description
Max
Unit
VTERM
Terminal Voltage with Respect to GND
–0.5 to +6.5
V
TSTG
Storage Temperature
–65 to +150
°C
IOUT
DC Output Current
–50 to +50
mA
IIK
Continuous Clamp Current,
–50
mA
IOK
VI < 0 or VO < 0
ICC
Continuous Current through each
±100
mA
ISS
VCC or GND
ABSOLUTE MAXIMUM RATINGS(1)
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
NOTE:
1. As applicable to the device type.
Symbol
Parameter(1)
Conditions
Typ.
Max.
Unit
CIN
Input Capacitance
VIN = 0V
4.5
6
pF
COUT
Output Capacitance
VOUT = 0V
6.5
8
pF
CI/O
I/O Port Capacitance
VIN = 0V
6.5
8
pF
CAPACITANCE (TA = +25°C, F = 1.0MHz)
NOTE:
1. These pins have "Bus-Hold". All other pins are standard inputs, outputs, or I/Os.
GND
1
A1
VCC
GND
VCC
CEAB
CLKAB
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
48
49
50
51
52
53
54
55
56
1
GND
VCC
GND
VCC
GND
25
26
27
28
32
31
30
29
OEAB
CLKAB
CEAB
1
A2
1
A3
1
A4
1
A5
1
A6
1
A7
1
A8
2
A1
2
A2
2
A3
2
A4
2
A5
2
A6
2
A7
2
A8
OEAB
CEBA
CLKBA
OEBA
CLKBA
CEBA
1
B1
1
B2
1
B3
1
B4
1
B5
1
B6
1
B7
1
B8
2
B1
2
B2
2
B3
2
B4
2
B5
2
B6
2
B7
2
B8
1
2
Pin Names
Description
xOEAB
A-to-B Output Enable Inputs (Active LOW)
xOEBA
B-to-A Output Enable Inputs (Active LOW)
xCEAB
A-to-B Clock Enable Inputs (Active LOW)
xCEBA
B-to-A Clock Enable Inputs (Active LOW)
xCLKAB
A-to-B Clock Inputs
xCLKBA
B-to-A Clock Inputs
xAx
A-to-B Data Inputs or B-to-A 3-State Outputs(1)
xBx
B-to-A Data Inputs or A-to-B 3-State Outputs(1)
PIN DESCRIPTION
FUNCTION TABLE(1,2)
Inputs
Outputs
xCEAB
xCLKAB
xOEAB
xAx
xBx
HX
L
X
B(3)
XL
L
X
B(3)
L
↑
LL
L
↑
LH
H
XX
H
X
Z
NOTES:
1. A-to-B data flow is shown: B-to-A data flow is similar but uses xCEBA, xCLKBA,
and xOEBA.
2. H = HIGH Voltage Level
L = LOW Voltage Level
X = Don’t Care
Z = High Impedance
↑ = LOW-to-HIGH Transition
3. Output level of B before the indicated steady-state input conditions were established.
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