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| 型号： | IDT74LVCH2244APY8 |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | 总线收发器 |
| 英文描述： | LVC/LCX/Z SERIES, DUAL 4-BIT DRIVER, TRUE OUTPUT, PDSO20 |
| 封装： | SSOP-20 |
| 文件页数： | 1/6页 |
| 文件大小： | 64K |
| 代理商： | IDT74LVCH2244APY8 |
INDUSTRIALTEMPERATURERANGE
IDT74LVC2244A
3.3VCMOSOCTALBUFFER/DRIVERWITH3-STATEOUTPUTS
1
FEBRUARY 2000
INDUSTRIAL TEMPERATURE RANGE
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
2000 Integrated Device Technology, Inc.
DSC-4886/1
FEATURES:
0.5 MICRON CMOS Technology
ESD > 2000V per MIL-STD-883, Method 3015; > 200V using
machine model (C = 200pF, R = 0)
VCC = 3.3V ± 0.3V, Normal Range
VCC = 2.7V to 3.6V, Extended Range
CMOS power levels (0.4
W typ. static)
Rail-to-rail output swing for increased noise margin
All inputs, outputs, and I/O are 5V tolerant
Supports hot insertion
Available in SOIC, SSOP, QSOP, and TSSOP packages
FUNCTIONAL BLOCK DIAGRAM
APPLICATIONS:
5V and 3.3V mixed voltage systems
Data communication and telecommunication systems
DRIVE FEATURES:
Balanced Output Drivers: ±12mA
Low switching noise
IDT74LVCH2244A
3.3V CMOS OCTAL
BUFFER/DRIVER WITH 3-
STATE OUTPUTS, 5 VOLT
TOLERANT I/O, BUS-HOLD
DESCRIPTION:
This octal buffer/driver is built using advanced dual metal CMOS technol-
ogy. The LVCH2244A device is organized as two 4-bit line drivers with
separateoutput-enable(OE)inputs.WhenOEislow,thedevicepassesdata
from the A inputs to the Y outputs. When OE is high, the outputs are in the
high-impedance state.
The LVCH2244A has series resistors in the device output structure which
will significantly reduce line noise when used with light loads. This driver has
been designed to drive ±12mA at the designated threshold levels.
Inputs can be driven from either 3.3V or 5V devices. This feature allows
theuseofthisdeviceasatranslatorinamixed3.3V/5Vsystemenvironment.
The LVCH2244A has “bus-hold” which retains the inputs’ last state
whenever the input goes to a high impedance. This prevents floating inputs
and eliminates the need for pull-up/down resistors.
1A1
1A2
1
A3
1
A4
1
Y1
1
Y2
1
Y3
1
Y4
1
2
4
6
8
18
16
14
12
1
OE
2
A1
2
A2
2
A3
2
A4
2
Y1
2
Y2
2
Y3
2
Y4
19
11
13
15
17
9
7
5
3
2
OE
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