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参数资料
| 型号： | IDT74LVCH373APG |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | 总线收发器 |
| 英文描述： | LVC/LCX/Z SERIES, 8-BIT DRIVER, TRUE OUTPUT, PDSO20 |
| 封装： | 0.65 MM PITCH, TSSOP-20 |
| 文件页数： | 1/6页 |
| 文件大小： | 63K |
| 代理商： | IDT74LVCH373APG |
1
EXTENDEDCOMMERCIALTEMPERATURERANGE
IDT74LVCH373A
3.3V CMOS OCTAL TRANSPARENT D-TYPE LATCH
OCTOBER 1999
1999
Integrated Device Technology, Inc.
DSC-4630/-
c
IDT74LVCH373A
EXTENDED COMMERCIAL TEMPERATURE RANGE
FEATURES:
– 0.5 MICRON CMOS Technology
– ESD > 2000V per MIL-STD-883, Method 3015;
> 200V using machine model (C = 200pF, R = 0)
– 1.27mm pitch SOIC, 0.65mm pitch SSOP,
0.635mm pitch QSOP, 0.65mm pitch TSSOP packages
– Extended commercial range of – 40°C to +85°C
–VCC = 3.3V ±0.3V, Normal Range
–VCC = 2.3V to 3.6V, Extended Range
– CMOS power levels (0.4W typ. static)
– Rail-to-Rail output swing for increased noise margin
– All inputs, outputs and I/O are 5 Volt tolerant
– Supports hot insertion
3.3V CMOS OCTAL
TRANSPARENT D-TYPE LATCH
WITH 3-STATE OUTPUTS, 5 VOLT
TOLERANT I/O AND BUS-HOLD
OE
C1
LE
1
D
TO SEVEN OTHER CHANNELS
1
11
3
2
1
D
1
Q
Drive Features for LVCH373A:
– High Output Drivers:
±24mA
– Reduced system switching noise
APPLICATIONS:
5V and 3.3V mixed voltage systems
Data communication and telecommunication systems
NO
T RECOMMENDED
FOR
NEW
DESIGNS
FOR
NEW
DESIGNS
FOR
NEW
DESIGNS
FOR
NEW
DESIGNS
FOR
NEW
DESIGNS
DESCRIPTION:
The LVCH373A octal transparent D-type latch is built using advanced
dual metal CMOS technology. While the latch-enable (LE) input is high, the
Q outputs follow the data (D) inputs. When LE is taken low, the Q outputs
are latched at the logic levels set up at the D inputs.
A buffered output-enable (OE) input can be used to place the eight
outputs in either a normal logic state (high or low logic levels) or a high-
impedance state. In the high-impedance state, the outputs neither load nor
drive the bus lines significantly. OE does not affect the internal operations
of the latches. Old data can be retained or new data can be entered while
the outputs are in the high-impedance state.
The LVCH373A has been designed with a ±24mA output driver. This
driver is capable of driving a moderate to heavy load while maintaining
speed performance.
Inputs can be driven from either 3.3V or 5V devices. This feature allows
the use of this device as a translator in a mixed 3.3V/5V system environ-
ment.
The LVCH373A has “bus-hold” which retains the inputs’ last state
whenever the input goes to a high impedance. This prevents floating inputs
and eliminates the need for pull-up/down resistors.
FUNCTIONAL BLOCK DIAGRAM
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