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参数资料
| 型号： | IDT74SSTUBF32869ABKG8 |
| 厂商： | IDT, Integrated Device Technology Inc |
| 文件页数： | 1/21页 |
| 文件大小： | 0K |
| 描述： | IC BUFFER 14BIT CONF DDR2 150BGA |
| 标准包装： | 2,000 |
| 逻辑类型： | 1:2 寄存缓冲器，带奇偶位 |
| 电源电压： | 1.7 V ~ 1.9 V |
| 位数： | 14 |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 150-TFBGA |
| 供应商设备封装： | 150-CABGA（8x13） |
| 包装： | 带卷 (TR) |
| 其它名称： | 74SSTUBF32869ABKG8 |
DATASHEET
14-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2
CONFIDENTIAL
IDT74SSTUBF32869A
14-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2
1
IDT74SSTUBF32869A
7093/10
CONFIDENTIAL
Description
The IDT74SSTUBF32869A is 14-bit 1:2 registered buffer
with parity, designed for 1.7 V to 1.9 V VDD operation.
All clock and data inputs are compatible with the JEDEC
standard for SSTL_18. The control inputs are LVCMOS. All
outputs are 1.8V CMOS drivers optimized to drive the
DDR2 DIMM load. They provide 50% more dynamic driver
strength than the standard SSTU32864 outputs.
The IDT74SSTUBF32869A operates from a differential
clock (CLK and CLK). Data are registered at the crossing of
CLK going high, and CLK going low.
The device supports low-power standby operation. When
the reset input (RESET) is low, the differential input
receivers are disabled, and undriven (floating) data, clock
and reference voltage (VREF) inputs are allowed. In
addition, when RESET is low all registers are reset, and all
outputs except PTYERR are forced low. The LVCMOS
RESET input must always be held at a valid logic high or
low level.
To ensure defined outputs from the register before a stable
clock has been supplied, RESET must be held in the low
state during power up.
In the DDR2 RDIMM application, RESET is specified to be
completely asynchronous with respect to CLK and CLK.
Therefore, no timing relationship can be guaranteed
between the two. When entering reset, the register will be
cleared and the outputs will be driven low quickly, relative to
the time to disable the differential input receivers. However,
when coming out of reset, the register will become active
quickly, relative to the time to enable the differential input
receivers. IDT74SSTUBF32869A must ensure that the
outputs remain low as long as the data inputs are low, the
clock is stable during the time from the low-to-high
transition of RESET and the input receivers are fully
enabled. This will ensures that there are no glitches on the
output.
The device monitors both DCS and CSR inputs and will
gate the Qn, PPO (Paritial-Parity-Out) and PTYERR (Parity
Error) Parity outputs from changing states when both DCS
and CSR are high. If either DCS and CSR input is low, the
Qn, PPO and PTYERR outputs will function normally. The
RESET input has priority over the DCS and CSR controls
and will force the Qn and PPO outputs low and the
PTYERR high.
The IDT74SSTUBF32869A includes a parity checking
function. The IDT74SSTUBF32869A accepts a parity bit
from the memory controller at its input pin PARIN one or
two cycles after the corresponding data input, compares it
with the data received on the D-inputs and indicates on its
opendrain PTYERR pin (active low) whether a parity error
has occurred. The number of cycles depends on the setting
of C1.
When used as a single device, the C1 input is tied low.
When used in pairs, the C1 inputs is tied low for the first
register (front) and the C1 input is tied high for the second
register. When used as a single register, the PPO and
PTYERR signals are produced two clock cycles after the
corresponding data input. When used in pairs, the PTYERR
signals of the first register are left floating. The PPO outputs
of the first register are cascaded to the PARIN signas on the
second register (back). The PPO and PTYERR signals of
the second register are produced three clock cycles after
the corresponding data input. Parity implimentation and
device wiring for single and dual die is described in the
diagram below.
If an error occurs, and the PTYERR is driven low, it stays
low for two clock cycles or until RESET is driven low. The
DIMM-dependent signals (DCKE, DCS, CSR and DODT)
are not included in the parity check computations.
All registers used on an individual DIMM must be of the
same configuration, i.e single or dual die.
Features
14-bit 1:2 registered buffer with parity check functionality
Supports SSTL_18 JEDEC specification on data inputs
and outputs
50% more dynamic driver strength than standard
SSTU32864
Supports LVCMOS switching levels on C1 and RESET
inputs
Low voltage operation: VDD = 1.7V to 1.9V
Available in 150 BGA package
Applications
DDR2 Memory Modules
Provides complete DDR DIMM solution with
ICS98ULPA877A or IDTCSPUA877A
Ideal for DDR2 667 and 800
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相关代理商/技术参数 |
参数描述 |
|---|---|
| IDT74SSTUBH32865ABKG | 功能描述:IC BUFFER 28BIT 1:2 REG 160-BGA RoHS:是 类别:集成电路 (IC) >> 逻辑 - 专用逻辑 系列:- 产品变化通告:Product Discontinuation 25/Apr/2012 标准包装:1,500 系列:74SSTV 逻辑类型:DDR 的寄存缓冲器 电源电压:2.3 V ~ 2.7 V 位数:14 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:48-TFSOP（0.240"，6.10mm 宽） 供应商设备封装:48-TSSOP 包装:带卷 (TR) |
| IDT74SSTUBH32865ABKG8 | 功能描述:IC BUFFER 28BIT 1:2 REG 160-BGA RoHS:是 类别:集成电路 (IC) >> 逻辑 - 专用逻辑 系列:- 产品变化通告:Product Discontinuation 25/Apr/2012 标准包装:1,500 系列:74SSTV 逻辑类型:DDR 的寄存缓冲器 电源电压:2.3 V ~ 2.7 V 位数:14 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:48-TFSOP（0.240"，6.10mm 宽） 供应商设备封装:48-TSSOP 包装:带卷 (TR) |
| IDT74SSTUBH32868ABKG | 功能描述:IC BUFFER 28BIT CONF DDR2 176BGA RoHS:是 类别:集成电路 (IC) >> 逻辑 - 专用逻辑 系列:- 产品变化通告:Product Discontinuation 25/Apr/2012 标准包装:1,500 系列:74SSTV 逻辑类型:DDR 的寄存缓冲器 电源电压:2.3 V ~ 2.7 V 位数:14 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:48-TFSOP（0.240"，6.10mm 宽） 供应商设备封装:48-TSSOP 包装:带卷 (TR) |
| IDT74SSTUBH32868ABKG8 | 功能描述:IC BUFFER 28BIT CONF DDR2 176BGA RoHS:是 类别:集成电路 (IC) >> 逻辑 - 专用逻辑 系列:- 产品变化通告:Product Discontinuation 25/Apr/2012 标准包装:1,500 系列:74SSTV 逻辑类型:DDR 的寄存缓冲器 电源电压:2.3 V ~ 2.7 V 位数:14 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:48-TFSOP（0.240"，6.10mm 宽） 供应商设备封装:48-TSSOP 包装:带卷 (TR) |
| IDT74SSTV16857PA | 制造商:Integrated Device Technology Inc 功能描述:SSTV SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PDSO48 |
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