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参数资料
| 型号： | IDT74SSTUBH32868ABKG8 |
| 厂商： | IDT, Integrated Device Technology Inc |
| 文件页数： | 1/22页 |
| 文件大小： | 0K |
| 描述： | IC BUFFER 28BIT CONF DDR2 176BGA |
| 标准包装： | 2,000 |
| 逻辑类型： | 1:1、1:2 可配置寄存缓冲器 |
| 电源电压： | 1.7 V ~ 1.9 V |
| 位数： | 28 |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 176-TFBGA |
| 供应商设备封装： | 176-CABGA（6x15） |
| 包装： | 带卷 (TR) |
| 其它名称： | 74SSTUBH32868ABKG8 |
DATASHEET
28-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2
IDT74SSTUBH32868A
28-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2
1
IDT74SSTUBH32868A
7105/7
Description
This 28-bit 1:2 configurable registered buffer is designed for
1.7V to 1.9V VDD operation. All inputs are compatible with
the JEDEC standard for SSTL_18, except the chip-select
gate-enable (CSGEN), control (C), and reset (RESET)
inputs, which are LVCMOS. All outputs are edge-controlled
circuits optimized for unterminated DIMM loads, and meet
SSTL_18 specifications, except the open-drain error
(QERR) output.
The IDT74SSTUBH32868A operates from a differential
clock (CLK and CLK). Data are registered at the crossing of
CLK going high and CLK going low. The device supports
low-power standby operation. When RESET is low, the
differential input receivers are disabled, and undriven
(floating) data, clock, and reference voltage (Vref) inputs
are allowed. In addition, when RESET is low, all registers
are reset and all outputs are forced low except QERR. The
LVCMOS RESET and C inputs must always be held at a
valid logic high or low level. To ensure defined outputs from
the register before a stable clock has been supplied,
RESET must be held in the low state during power up. In
the DDR2 RDIMM application, RESET is specified to be
completely asynchronous with respect to CLK and CLK.
Therefore, no timing relationship can be ensured between
the two. When entering reset, the register will be cleared
and the data outputs will be driven low quickly, relative to
the time to disable the differential input receivers. However,
when coming out of reset, the register will become active
quickly, relative to the time to enable the differential input
receivers. As long as the data inputs are low, and the clock
is stable during the time from the low-to-high transition of
RESET until the input receivers are fully enabled, the
design of the IDT74SSTUBH32868A must ensure that the
outputs will remain low, thus ensuring no glitches on the
output.
The IDT74SSTUBH32868A includes a parity checking
function. Parity, which arrives one cycle after the data input
to which it applies, is checked on the PAR_IN input of the
device. The corresponding QERR output signal for the data
inputs is generated two clock cycles after the data, to which
the QERR signal applies, is registered. The
IDT74SSTUBH32868A accepts a parity bit from the
memory controller on the parity bit (PAR_IN) input,
compares it with the data received on the
DIMM-independent D-inputs (D1-D5, D7, D9-D12,
D17-D28 when C = 0; or D1-D12, D17-D20, D22, D24-D28
when C = 1) and indicates whether a parity error has
occurred on the open-drain QERR pin (active low). The
convention is even parity, i.e., valid parity is defined as an
even number of ones across the DIMM-independent data
inputs combined with the parity input bit. To calculate parity,
all DIMM-independent D-inputs must be tied to a known
logic state. If an error occurs and the QERR output is driven
low, it stays latched low for a minimum of two clock cycles or
until RESET is driven low. If two or more consecutive parity
errors occur, the QERR output is driven low and latched low
for a clock duration equal to the parity error duration or until
RESET is driven low. If a parity error occurs on the clock
cycle before the device enters the low-power (LPM) and the
QERR output is driven low, then it stays lateched low for the
LPM duration plus two clock cycles or until RESET is driven
low. The DIMM-dependent signals (DCKE0, DCKE1,
DODT0, DODT1, DCS0 and DCS1) are not included in the
parity check computation.
The C input controls the pinout configuration from
register-A configuration (when low) to register-B
configuration (when high). The C input should not be
switched during normal operation. It should be hardwired to
a valid low or high level to configure the register in the
desired mode. The device also supports low-power active
operation by monitoring both system chip select (DCS0 and
DCS1) and CSGEN inputs and will gate the Qn outputs
from changing states when CSGEN, DCS0, and DCS1
inputs are high. If CSGEN, DCS0 orDCS1 input is low, the
Qn outputs will function normally. Also, if both DCS0 and
DCS1 inputs are high, the device will gate the QERR output
from changing states. If either DCS0 orDCS1 is low, the
QERR output will function normally. The RESET input has
priority over the DCS0 and DCS1 control and when driven
low will force the Qn outputs low, and the QERR output
high. If the chip-select control functionality is not desired,
then the CSGEN input can be hard-wired to ground, in
which case, the setup-time requirement for DCS0 and
DCS1 would be the same as for the other D data inputs. To
control the low-power mode with DCS0 and DCS1 only,
then the CSGEN input should be pulled up to Vdd through a
pullup resistor. The two VREF pins (A1 and V1) are
connected together internally by approximately 150.
However, it is necessary to connect only one of the two
VREF pins to the external VREF power supply. An unused
VREF pin should be terminated with a VREF coupling
capacitor.
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