参数资料
型号: IDT79RC32H434-266BCI
厂商: IDT, Integrated Device Technology Inc
文件页数: 28/53页
文件大小: 0K
描述: IC MPU 32BIT CORE 266MHZ 256-BGA
标准包装: 90
系列: Interprise™
处理器类型: MIPS32 32-位
速度: 266MHz
电压: 1.2V
安装类型: 表面贴装
封装/外壳: 256-LBGA
供应商设备封装: 256-CABGA(17x17)
包装: 托盘
其它名称: 79RC32H434-266BCI
34 of 53
January 19, 2006
IDT RC32434
Using the EJTAG Probe
In Figure 20, the pull-up resistors for JTAG_TDO and RST*, the pull-down resistor for JTAG_TRST_N, and the series resistor for JTAG_TDO must
be adjusted to the specific design. However, the recommended pull-up/down resistor is 1.0 k
because a low value reduces crosstalk on the cable to
the connector, allowing higher JTAG_TCK frequencies. A typical value for the series resistor is 33
. Recommended resistor values have ± 5% toler-
ance.
If a probe is used, the pull-up resistor on JTAG_TDO must ensure that the JTAG_TDO level is high when no probe is connected and the
JTAG_TDO output is tri-stated. This requirement allows reliable connection of the probe if it is hooked-up when the power is already on (hot plug). The
pull-up resistor value of around 47 k
should be sufficient. Optional diodes to protect against overshoot and undershoot voltage can be added on the
signals of the chip with EJTAG.
If a probe is used, the RST* signal must have a pull-up resistor because it is controlled by an open-collector (OC) driver in the probe, and thus is
actively pulled low only. The pull-up resistor is responsible for the high value when not driven by the probe of 25pF. The input on the target system
reset circuit must be able to accept the rise time when the pull-up resistor charges the capacitance to a high logical level. Vcc I/O must connect to a
voltage reference that drops rapidly to below 0.5V when the target system loses power, even with a capacitive load of 25pF. The probe can thus detect
the lost power condition.
For additional information on EJTAG, refer to Chapter 17 of the RC32434 User Reference Manual.
P
PP
Phase-Locked Loop (PLL)
hase-Locked Loop (PLL)
The phase-locked loop (PLL) multiplies the external oscillator input (pin CLK) according to the parameter provided by the boot configuration vector
to create the processor clock (PCLK). Inherently, PLL circuits are only capable of generating clock frequencies within a limited range.
PLL Filters
It is recommended that the system designer provide a filter network of passive components for the PLL analog and digital power supplies. The PLL
circuit power and PLL circuit ground should be isolated from power and ground with a filter circuit such as the one shown in Figure 21. Because the
optimum values for the filter components depend upon the application and the system noise environment, these values should be considered as
starting points for further experimentation within your specific application.
Figure 21 PLL Filter Circuit for Noisy Environments
10
F0.1 F
100 pF
Vcc
Vss
VccPLL
VssPLL
10 ohm1
RC32434
VccPLL
VssPLL
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