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IDT82P2281
SINGLE T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
Functional Description
70
August 20, 2009
the pulse on the RSFS is determined by the FE bit. The active edge of
the RSCK used to update the data on the RSD and RSIG is determined
by the DE bit. If the FE bit and the DE bit are not equal, the pulse on the
RSFS is ahead. The speed of the RSCK can be selected by the CMS bit
to be the same rate as the data rate on the system side (2.048 MHz) or
double the data rate (4.096 MHz). If the speed of the RSCK is double
the data rate, there will be two active edges in one bit duration. In this
case, the EDGE bit determines the active edge to update the data on the
RSD and RSIG pins. The pulse on the RSFS pin is always sampled on
its first active edge.
In the Receive Clock Slave mode, the RSFS asserts at a rate of
integer multiple of 125
s to indicate the start of a frame. The active
polarity of the RSFS is selected by the FSINV bit. If the pulse on the
RSFS pin is not an integer multiple of 125
s, this detection will be indi-
cated by the RCOFAI bit. If the RCOFAE bit is enabled, an interrupt will
be reported by the INT pin when the RCOFAI bit is ‘1’.
3.17.2.3
Receive Multiplexed Mode
In the Receive Multiplexed mode, one multiplexed bus is used to
output the data from the link. The data of the link is byte-interleaved out-
put on the multiplexed bus. When the data from the link is output on one
multiplexed bus, the position of the data is arranged by setting the
timeslot offset.
In the Receive Multiplexed mode, the timing signal on the MRSCK
pin and the framing pulse on the MRSFS pin are provided by the system
side. The signaling bits on the MRSIG pin are per-timeslot aligned with
the corresponding data on the MRSD pin.
In the Receive Multiplexed mode, the data on the system interface
is clocked by the MRSCK. The active edge of the MRSCK used to sam-
ple the pulse on the MRSFS is determined by the FE bit. The active
edge of the MRSCK used to update the data on the MRSD and MRSIG
is determined by the DE bit. If the FE bit and the DE bit are not equal,
the pulse on the MRSFS is ahead. The MRSCK can be selected by the
CMS bit to be the same rate as the data rate on the system side (8.192
MHz) or double the data rate (16.384 MHz). If the speed of the MRSCK
is double the data rate, there will be two active edges in one bit duration.
In this case, the EDGE bit determines the active edge to update the data
on the MRSD and MRSIG pins. The pulse on the MRSFS pin is always
sampled on its first active edge.
In the Receive Multiplexed mode, the MRSFS asserts at a rate of
integer multiple of 125
s to indicate the start of a frame. The active
polarity of the MRSFS is selected by the FSINV bit. If the pulse on the
MRSFS pin is not an integer multiple of 125
s, this detection will be
indicated by the RCOFAI bit. If the RCOFAE bit is enabled, an interrupt
will be reported by the INT pin when the RCOFAI bit is ‘1’.
3.17.2.4
Offset
Except that in the Receive Master mode, when the OHD bit, the
SMFS bit and the CMFS bit are set to TS1 and TS16 overhead indica-
tion, the bit offset and timeslot offset are both supported in all the other
conditions. The offset is between the framing pulse on RSFS/MRSFS
pin and the start of the corresponding frame output on the RSD/MRSD
pin. The signaling bits on the RSIG/MRSIG pin are always per-timeslot
aligned with the data on the RSD/MRSD pin.
different operating modes and the configuration of the offset.
In Non-multiplexed mode, the timeslot offset can be configured
from 0 to 31 timeslots (0 & 31 are included). In Multiplexed mode, the
timeslot offset can be configured from 0 to 127 timeslots (0 & 127 are
included).
3.17.2.5
Output On RSD/MRSD & RSIG/MRSIG
The output on the RSD/MRSD and the RSIG/MRSIG pins can be
configured by the TRI bit to be in high impedance state or to output the
processed data stream.
Bit
Register
Address (Hex)
RMUX
Backplane Global Configuration
010
RMODE
RBIF Mode
047
MAP[1:0] (T1/J1
only)
G56K
ID * - Channel Control (for T1/
J1) / Timeslot Control (for E1)
RPLC ID - 01~18 (for
T1/J1) / 00~1F (for E1)
GAP
FBITGAP (T1/J1
only)
RBIF Operation
046
FE
DE
CMS
TRI
PCCE
RPLC Control Enable
0D1
CMFS
RBIF Frame Pulse
048
ALTIFS (T1/J1 only)
FSINV
OHD (E1 only)
SMFS (E1 only)
EDGE
RBIF Bit Offset
04A
BOFF[2:0]
RCOFAI
RTSFS Change Indication
04BH
RCOFAE
RTSFS Interrupt Control
04C
TSOFF[6:0]
RBIT TS Offset
049
Note:
*
ID means Indirect Register in the Receive Payload Control function block.