- 您现在的位置：买卖IC网 > PDF目录377488 > IDT82P2282 (Integrated Device Technology, Inc.) Dual T1/E1/J1 Long Haul / Short Haul Transceiver PDF资料下载
参数资料
| 型号： | IDT82P2282 |
| 厂商： | Integrated Device Technology, Inc. |
| 英文描述： | Dual T1/E1/J1 Long Haul / Short Haul Transceiver |
| 中文描述： | 双T1/E1/J1收发长途/短途收发器 |
| 文件页数： | 36/375页 |
| 文件大小： | 2430K |
| 代理商： | IDT82P2282 |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页当前第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页第63页第64页第65页第66页第67页第68页第69页第70页第71页第72页第73页第74页第75页第76页第77页第78页第79页第80页第81页第82页第83页第84页第85页第86页第87页第88页第89页第90页第91页第92页第93页第94页第95页第96页第97页第98页第99页第100页第101页第102页第103页第104页第105页第106页第107页第108页第109页第110页第111页第112页第113页第114页第115页第116页第117页第118页第119页第120页第121页第122页第123页第124页第125页第126页第127页第128页第129页第130页第131页第132页第133页第134页第135页第136页第137页第138页第139页第140页第141页第142页第143页第144页第145页第146页第147页第148页第149页第150页第151页第152页第153页第154页第155页第156页第157页第158页第159页第160页第161页第162页第163页第164页第165页第166页第167页第168页第169页第170页第171页第172页第173页第174页第175页第176页第177页第178页第179页第180页第181页第182页第183页第184页第185页第186页第187页第188页第189页第190页第191页第192页第193页第194页第195页第196页第197页第198页第199页第200页第201页第202页第203页第204页第205页第206页第207页第208页第209页第210页第211页第212页第213页第214页第215页第216页第217页第218页第219页第220页第221页第222页第223页第224页第225页第226页第227页第228页第229页第230页第231页第232页第233页第234页第235页第236页第237页第238页第239页第240页第241页第242页第243页第244页第245页第246页第247页第248页第249页第250页第251页第252页第253页第254页第255页第256页第257页第258页第259页第260页第261页第262页第263页第264页第265页第266页第267页第268页第269页第270页第271页第272页第273页第274页第275页第276页第277页第278页第279页第280页第281页第282页第283页第284页第285页第286页第287页第288页第289页第290页第291页第292页第293页第294页第295页第296页第297页第298页第299页第300页第301页第302页第303页第304页第305页第306页第307页第308页第309页第310页第311页第312页第313页第314页第315页第316页第317页第318页第319页第320页第321页第322页第323页第324页第325页第326页第327页第328页第329页第330页第331页第332页第333页第334页第335页第336页第337页第338页第339页第340页第341页第342页第343页第344页第345页第346页第347页第348页第349页第350页第351页第352页第353页第354页第355页第356页第357页第358页第359页第360页第361页第362页第363页第364页第365页第366页第367页第368页第369页第370页第371页第372页第373页第374页第375页
IDT82P2281
SINGLE T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
Functional Description
25
October 7, 2003
3.8.1.2
Error Event And Out Of Synchronization Detection
After the frame is in synchronization, the Frame Processor contin-
ues to monitor the received data stream to detect errors and judge if it is
out of synchronization.
3.8.1.2.1
Super Frame (SF) Format
In SF format, two kinds of errors are detected:
1. Severely Ft Bit Error: Each received Ft bit is compared with the
expected one (refer to Table 12). Each unmatched Ft bit leads to an Ft
bit error event. When 2 or more Ft bit errors are detected in a 6-basic-
frame fixed window, the severely Ft bit error occurs. This error event is
captured by the SFEI bit.
2. F Bit Error: Each received F bit is compared with the expected
one (refer to Table 12). Each unmatched F bit leads to an F bit error
event. This error event is captured by the FERI bit and is forwarded to
the Performance Monitor.
When the F Bit Error number exceeds the ratio set in the M2O[1:0]
bits, it is out of synchronization. Then if the REFEN bit is ‘1’, the Frame
Processor will start to search for synchronization again. If the REFEN bit
is ‘0’, no error can lead to reframe except for manually setting. The man-
ual reframe is executed by a transition from ‘0’ to ‘1’ on the REFR bit.
During out of synchronization state, the error event detection is sus-
pended.
Once resynchronized, if the new-found F bit position differs from
the previous one, the change of frame alignment event is generated.
This event is captured by the COFAI bit and is forwarded to the Perfor-
mance Monitor.
3.8.1.2.2
Extended Super Frame (ESF) Format
In ESF format, four kinds of errors are detected:
1. Frame Alignment Bit Error: Each received Frame Alignment bit is
compared with the expected one (refer to Table 13). Each unmatched bit
leads to a frame alignment bit error event. This error event is captured
by the FERI bit and is forwarded to the Performance Monitor.
2. CRC-6 Error: When the local calculated CRC-6 of the current
received ESF frame does not match the received CRC-6 of the next
received ESF frame, a single CRC-6 error event is generated. This error
event is captured by the BEEI bit and is forwarded to the Performance
Monitor.
3. Excessive CRC-6 Error: Once the accumulated CRC-6 errors
exceed 319 occasions (> 319) in a 1 second fixed window, an excessive
CRC-6 error event is generated. This error event is captured by the
EXCRCERI bit and is forwarded to the Performance Monitor.
4. Severely Frame Alignment Bit Error: When 2 or more frame
alignment bit errors are detected in a 1-ESF-frame fixed window, the
severely frame alignment bit error occurs. This error event is captured
by the SFEI bit.
When the Frame Alignment Bit Error number exceeds the ratio set
in the M2O[1:0] bits, it is out of synchronization. Then if the REFEN bit is
‘1’, the Frame Processor will start to search for synchronization again.
Additionally, the Excessive CRC-6 Error also leads to out of ESF syn-
chronization. In this condition, both the REFEN bit being ‘1’ and the
REFCRCE bit being ‘1’ will allow the Frame Processor to search for syn-
chronization again. If the REFEN bit is ‘0’, no error can lead to reframe
except for manually setting. The manual reframe is executed by a transi-
tion from ‘0’ to ‘1’ on the REFR bit. During out of synchronization state,
the error event detection is suspended.
Once resynchronized, if the new-found F bit position differs from
the previous one, the change of frame alignment event is generated.
This event is captured by the COFAI bit and is forwarded to the Perfor-
mance Monitor.
3.8.1.2.3
T1 Digital Multiplexer (DM) Format (T1 only)
In T1 DM format, three kinds of errors are detected:
1. Severely Ft Bit Error: Each received Ft bit is compared with the
expected one (refer to Table 14). Each unmatched Ft bit leads to an Ft
bit error event. When 2 or more Ft bit errors are detected in a 6-basic-
frame fixed window, the severely Ft bit error occurs. This error event is
captured by the SFEI bit.
2. F Bit Error: Each received F bit is compared with the expected
one (refer to Table 14). Each unmatched F bit leads to an F bit error
event. This error event is captured by the FERI bit and is forwarded to
the Performance Monitor.
3. DDS Pattern Error: The received 6-bit DDS in each CH24 is
compared with the DDS pattern - ‘0XX11101’ (MSB left and ‘X’ is not
cared). When one or more bits do not match the DDS pattern, a single
DDS pattern error event is generated. This error event is forwarded to
the Performance Monitor.
The 6-bit DDS pattern and its following F-bit make up a 7-bit pat-
tern. When one or more bits do not match its pattern (refer to Table 14),
a single error is generated. When this error number exceeds the ratio
set in the M2O[1:0] bits, it is out of synchronization. Then if the REFEN
bit is ‘1’, the Frame Processor will start to search for synchronization
again. If the REFEN bit is ‘0’, no error can lead to reframe except for
manually setting. The manual reframe is executed by a transition from
‘0’ to ‘1’ on the REFR bit. During out of synchronization state, the error
event detection is suspended.
Once resynchronized, if the new-found F bit position differs from
the previous one, the change of frame alignment event is generated.
This event is captured by the COFAI bit and is forwarded to the Perfor-
mance Monitor.
3.8.1.2.4
Switch Line Carrier - 96 (SLC-96) Format (T1 only)
In SLC-96 format, only one kind of error is detected:
1. F Bit Error: The Ft bit in each odd frame and the Fs bit in Frame
(2n) (0<n<12 and n=36) is compared with the expected one (refer to
Table 15). Each unmatched bit leads to a F-bit error event. This error
event is captured by the FERI bit and is forwarded to the Performance
Monitor.
Each unmatched Ft bit in the odd frame and each unmatched Fs bit
in Frame (2n) (0<n<12 and n=36) are also counted separately. When the
number of either of them exceeds the ratio set in the M2O[1:0] bits, it is
out of synchronization. Then if the REFEN bit is ‘1’, the Frame Proces-
sor will start to search for synchronization again. If the REFEN bit is ‘0’,
no error can lead to reframe except for manually setting. The manual
reframe is executed by a transition from ‘0’ to ‘1’ on the REFR bit. During
out of synchronization state, the error event detection is suspended.
相关PDF资料 |
PDF描述 |
|---|---|
| IDT82P2282PK | Dual T1/E1/J1 Long Haul / Short Haul Transceiver |
| IDT82P2288BB | Octal T1/E1/J1 Long Haul Short Haul Transceiver |
| IDT82V2088BB | OCTAL CHANNEL T1/E1/J1 LONG HAUL/ SHORT HAUL LINE INTERFACE UNIT |
| IDT82V2058DA | OCTAL E1 SHORT HAUL LINE INTERFACE UNIT |
| IDT82V2608BB | INVERSE MULTIPLEXING FOR ATM |
相关代理商/技术参数 |
参数描述 |
|---|---|
| IDT82P2282_09 | 制造商:IDT 制造商全称:Integrated Device Technology 功能描述:Dual T1/E1/J1 Long Haul / Short Haul Transceiver |
| IDT82P2282PF | 功能描述:TXRX T1/J1/E1 2CHAN 100-TQFP RoHS:否 类别:集成电路 (IC) >> 接口 - 驱动器，接收器，收发器 系列:- 标准包装:250 系列:- 类型:收发器 驱动器/接收器数:2/2 规程:RS232 电源电压:3 V ~ 5.5 V 安装类型:表面贴装 封装/外壳:16-TSSOP（0.173"，4.40mm 宽） 供应商设备封装:16-TSSOP 包装:带卷 (TR) |
| IDT82P2282PF8 | 功能描述:TXRX T1/J1/E1 2CHAN 100-TQFP RoHS:否 类别:集成电路 (IC) >> 接口 - 驱动器，接收器，收发器 系列:- 标准包装:250 系列:- 类型:收发器 驱动器/接收器数:2/2 规程:RS232 电源电压:3 V ~ 5.5 V 安装类型:表面贴装 封装/外壳:16-TSSOP（0.173"，4.40mm 宽） 供应商设备封装:16-TSSOP 包装:带卷 (TR) |
| IDT82P2282PFBLANK | 制造商:IDT 制造商全称:Integrated Device Technology 功能描述:Dual T1/E1/J1 Long Haul / Short Haul Transceiver |
| IDT82P2282PFG | 功能描述:IC TXRX T1/J1/E1 2CH 100TQFP RoHS:是 类别:集成电路 (IC) >> 接口 - 驱动器，接收器，收发器 系列:- 标准包装:2,500 系列:- 类型:驱动器 驱动器/接收器数:4/0 规程:RS422 电源电压:4.5 V ~ 5.5 V 安装类型:表面贴装 封装/外壳:16-SOIC（0.154"，3.90mm 宽） 供应商设备封装:16-SOIC N 包装:带卷 (TR) |
发布紧急采购，3分钟左右您将得到回复。