参数资料
型号: IDT82P2288BB
厂商: INTEGRATED DEVICE TECHNOLOGY INC
元件分类: 数字传输电路
英文描述: Octal T1/E1/J1 Long Haul Short Haul Transceiver
中文描述: DATACOM, PCM TRANSCEIVER, PBGA256
封装: PLASTIC, BGA-256
文件页数: 64/375页
文件大小: 2430K
代理商: IDT82P2288BB
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IDT82P2281
SINGLE T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
Functional Description
53
October 7, 2003
3.17
RECEIVE SYSTEM INTERFACE
The Receive System Interface determines how to output the
received data stream to the system backplane. The timing clocks and
framing pulses can be provided by the system backplane or obtained
from the far end. The Receive System Interface supports various config-
urations to meet various requirements in different applications.
3.17.1
T1/J1 MODE
In T1/J1 mode, the Receive System Interface can be set in Non-
multiplexed Mode or Multiplexed Mode. In the Non-multiplexed Mode,
the RSD pin is used to output the received data at the bit rate of 1.544
Mb/s or 2.048 Mb/s (T1/J1 mode E1 rate). While in the Multiplexed
Mode, the received data from the link is converted to 2.048 Mb/s format
and byte interleaved to form one high speed data stream and output on
the MRSD pin at the bit rate of 8.192 Mb/s.
In the Non-multiplexed Mode, if the receive system interface and
the receive line side are timed to a same clock source, the Receive Sys-
tem Interface is in Receive Clock Master mode. If the receive system
interface and the receive line side are timed to different clock sources,
the Receive System Interface is in Receive Clock Slave mode.
In the Receive Clock Master mode, if RSCK outputs pulses during
the entire T1/J1 frame, the Receive System Interface is in Receive Clock
Master Full T1/J1 mode. If only the clocks aligned to the selected chan-
nels are output on RSCK, the Receive System Interface is in Receive
Clock Master Fractional T1/J1 mode.
In the Receive Clock Slave mode, the backplane data rate may be
equal to 1.544 Mb/s (i.e., the line data rate) or 2.048 Mb/s. If the back-
plane data rate is 2.048 Mb/s, the Receive System Interface is in T1/J1
mode E1 rate and the received data stream (1.544 Mb/s) should be
mapped per 3 kinds of schemes.
In the Receive Multiplexed mode, since the received data should
be converted to 2.048 Mb/s format first and then multiplexed to 8.192
Mb/s, there are still 3 kinds of schemes to be selected.
Table 39 summarizes how to set the Receive System Interface into
various operating modes and the pins’ direction of the Receive System
Interface in different operating modes.
3.17.1.1
Receive Clock Master Mode
In the Receive Clock Master mode, the timing signal on the RSCK
pin and framing pulse on the RSFS pin are used to output the data on
the RSD pin. The signaling bits on the RSIG pin are per-channel aligned
with the data on the RSD pin.
In the Receive Clock Master mode, the data on the system inter-
face is clocked by the RSCK. The active edge of the RSCK used to
update the pulse on the RSFS is determined by the FE bit. The active
edge of the RSCK used to update the data on the RSD and RSIG is
determined by the DE bit. If the FE bit and the DE bit are not equal, the
pulse on the RSFS is ahead.
In the Receive Clock Master mode, the RSFS can indicate each F-
bit or the first F-bit of every SF/ESF/T1 DM/SLC-96 multi-frame. In SF
format, the RSFS can also indicate every second F-bit or the first F-bit of
every second SF multi-frame. All the indications are selected by the
CMFS bit and the ALTIFS bit. The active polarity of the RSFS is selected
by the FSINV bit.
The Receive Clock Master mode includes two sub-modes: Receive
Clock Master Full T1/J1 mode and Receive Clock Master Fractional T1/
J1 mode.
3.17.1.1.1
Besides all the common functions described in the Receive Clock
Master mode, the special feature in this mode is that the RSCK is a
standard 1.544 MHz clock, and the data in the F-bit and all 24 channels
in a standard T1/J1 frame are clocked out by the RSCK.
Receive Clock Master Full T1/J1 Mode
3.17.1.1.2
Besides all the common functions described in the Receive Clock
Master mode, the special feature in this mode is that the RSCK is a
gapped 1.544 MHz clock (no clock signal during the selected position).
Receive Clock Master Fractional T1/J1 Mode
Table 39: Operating Modes Selection In T1/J1 Receive Path
RMUX RMODE
G56K, GAP /
FBITGAP
MAP[1:0]
2
Operating Mode
Receive System Interface Pin
Input
Output
0
0
00 / 0
not all 0s
1
X
Receive Clock Master Full T1/J1
Receive Clock Master Fractional T1/J1
X
RSCK, RSFS,
RSD, RSIG
1
X
00
01
10
11
01
10
11
Receive Clock Slave - T1/J1 Rate
Receive Clock Slave - T1/J1 Mode E1 Rate per G.802
Receive Clock Slave - T1/J1 Mode E1 Rate per One Filler Every Four CHs
Receive Clock Slave - T1/J1 Mode E1 Rate per Continuous CHs
Receive Multiplexed - T1/J1 Mode E1 Rate per G.802
Receive Multiplexed - T1/J1 Mode E1 Rate per One Filler Every Four CHs
Receive Multiplexed - T1/J1 Mode E1 Rate per Continuous CHs
RSCK, RSFS
RSD, RSIG
1
X
X
MRSCK, MRSFS
MRSD, MRSIG
NOTE:
1. When the G56K, GAP bits in RPLC indirect registers are set, the PCCE bit must be set to ‘1’.
2. The MAP[1:0] bits can not be set to ‘00’ in the Receive Multiplexed mode.
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