- 您现在的位置：买卖IC网 > PDF目录377488 > IDT82V3255TFG (INTEGRATED DEVICE TECHNOLOGY INC) WAN PLL PDF资料下载
参数资料
| 型号： | IDT82V3255TFG |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | 通信及网络 |
| 英文描述： | WAN PLL |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, PQFP64 |
| 封装： | GREEN, TQFP-64 |
| 文件页数： | 21/127页 |
| 文件大小： | 868K |
| 代理商： | IDT82V3255TFG |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页当前第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页第63页第64页第65页第66页第67页第68页第69页第70页第71页第72页第73页第74页第75页第76页第77页第78页第79页第80页第81页第82页第83页第84页第85页第86页第87页第88页第89页第90页第91页第92页第93页第94页第95页第96页第97页第98页第99页第100页第101页第102页第103页第104页第105页第106页第107页第108页第109页第110页第111页第112页第113页第114页第115页第116页第117页第118页第119页第120页第121页第122页第123页第124页第125页第126页第127页
IDT82V3255
WAN PLL
Functional Description
21
June 19, 2006
3.5.2
FREQUENCY MONITORING
Frequency is monitored by comparing the input clock with a refer-
ence clock. The reference clock can be derived from the master clock or
the output of T0 DPLL, as determined by the FREQ_MON_CLK bit.
A frequency hard alarm threshold is set for frequency monitoring. If
the FREQ_MON_HARD_EN bit is ‘1’, a frequency hard alarm is raised
when the frequency of the input clock with respect to the reference clock
is above the threshold; the alarm is cleared when the frequency is below
the threshold.
The frequency hard alarm threshold can be calculated as follows:
Frequency Hard Alarm Threshold (ppm) = (ALL_FREQ_HARD_
THRESHOLD[3:0] + 1) X FREQ_MON_FACTOR[3:0]
If the FREQ_MON_HARD_EN bit is ‘1’, the frequency hard alarm
status
of
the
input
clock
INn_CMOS_FREQ_HARD_ALARM bit (n = 1, 2 or 3) /
INn_DIFF_FREQ_HARD_ALARM bit (n = 1 or 2). When the
FREQ_MON_HARD_EN bit is ‘0’, no frequency hard alarm is raised
even if the input clock is above the frequency hard alarm threshold.
is
indicated
by
the
The input clock with a frequency hard alarm is disqualified for clock
selection for T0/T4 DPLL.
In addition, if the input clock is 2 kHz, 4 kHz or 8 kHz, its clock edges
with respect to the reference clock are monitored. If any edge drifts out-
side ±5%, the input clock is disqualified for clock selection for T0/T4
DPLL. The input clock is qualified if any edge drifts inside ±5%. This
function is supported only when the IN_NOISE_WINDOW bit is ‘1’.
The frequency of each input clock with respect to the reference clock
can be read by doing the following step by step:
1. Select an input clock by setting the IN_FREQ_READ_CH[3:0]
bits;
2. Read the value in the IN_FREQ_VALUE[7:0] bits and calculate
as follows:
Input Clock Frequency (ppm) = IN_FREQ_VALUE[7:0] X
FREQ_MON_FACTOR[3:0]
Note that the value set by the FREQ_MON_FACTOR[3:0] bits
depends on the application.
Table 5: Related Bit / Register in Chapter 3.5
Bit
Register
Address (Hex)
BUCKET_SIZE_n_DATA[7:0] (3
≥
n
≥
0)
UPPER_THRESHOLD_n_DATA[7:0] (3
≥
n
≥
0)
LOWER_THRESHOLD_n_DATA[7:0] (3
≥
n
≥
0)
DECAY_RATE_n_DATA[1:0] (3
≥
n
≥
0)
BUCKET_SIZE_0_CNFG ~ BUCKET_SIZE_3_CNFG
UPPER_THRESHOLD_0_CNFG ~ UPPER_THRESHOLD_3_CNFG
LOWER_THRESHOLD_0_CNFG ~ LOWER_THRESHOLD_3_CNFG
DECAY_RATE_0_CNFG ~ DECAY_RATE_3_CNFG
IN1_CMOS_CNFG, IN2_CMOS_CNFG, IN1_DIFF_CNFG,
IN2_DIFF_CNFG, IN3_CMOS_CNFG
33, 37, 3B, 3F
31, 35, 39, 3D
32, 36, 3A, 3E
34, 38, 3C, 40
BUCKET_SEL[1:0]
16, 17, 19, 1A, 1D
INn_CMOS_NO_ACTIVITY_ALARM (n = 1, 2, or 3)
INn_CMOS_FREQ_HARD_ALARM (n = 1, 2 or 3)
INn_DIFF_NO_ACTIVITY_ALARM (n = 1 or 2)
INn_DIFF_FREQ_HARD_ALARM (n = 1 or 2)
FREQ_MON_CLK
FREQ_MON_HARD_EN
ALL_FREQ_HARD_THRESHOLD[3:0]
FREQ_MON_FACTOR[3:0]
IN_NOISE_WINDOW
IN_FREQ_READ_CH[3:0]
IN_FREQ_VALUE[7:0]
IN1_IN2_CMOS_STS, IN3_CMOS_STS
44, 47
IN1_IN2_DIFF_STS
45
MON_SW_PBO_CNFG
0B
ALL_FREQ_MON_THRESHOLD_CNFG
FREQ_MON_FACTOR_CNFG
PHASE_MON_PBO_CNFG
IN_FREQ_READ_CH_CNFG
IN_FREQ_READ_STS
2F
2E
78
41
42
相关PDF资料 |
PDF描述 |
|---|---|
| IDT82V3280 | WAN PLL |
| IDT82V3280DQ | WAN PLL |
| IDT82V3280DQG | WAN PLL |
| IDT82V3280PF | WAN PLL |
| IDT82V3280PFG | WAN PLL |
相关代理商/技术参数 |
参数描述 |
|---|---|
| IDT82V3255TFG8 | 功能描述:IC PLL WAN SMC STRATUM 3 64-TQFP RoHS:是 类别:集成电路 (IC) >> 时钟/计时 - 专用 系列:- 标准包装:1,500 系列:- 类型:时钟缓冲器/驱动器 PLL:是 主要目的:- 输入:- 输出:- 电路数:- 比率 - 输入:输出:- 差分 - 输入:输出:- 频率 - 最大:- 电源电压:3.3V 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:28-SSOP（0.209"，5.30mm 宽） 供应商设备封装:28-SSOP 包装:带卷 (TR) 其它名称:93786AFT |
| IDT82V3255TFGBLANK | 制造商:IDT 制造商全称:Integrated Device Technology 功能描述:WAN PLL |
| IDT82V3280 | 制造商:IDT 制造商全称:Integrated Device Technology 功能描述:WAN PLL |
| IDT82V3280_08 | 制造商:IDT 制造商全称:Integrated Device Technology 功能描述:WAN PLL |
| IDT82V3280APFG | 功能描述:IC PLL WAN SE STRATUM 2 100TQFP RoHS:是 类别:集成电路 (IC) >> 时钟/计时 - 专用 系列:- 标准包装:1,500 系列:- 类型:时钟缓冲器/驱动器 PLL:是 主要目的:- 输入:- 输出:- 电路数:- 比率 - 输入:输出:- 差分 - 输入:输出:- 频率 - 最大:- 电源电压:3.3V 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:28-SSOP（0.209"，5.30mm 宽） 供应商设备封装:28-SSOP 包装:带卷 (TR) 其它名称:93786AFT |
发布紧急采购，3分钟左右您将得到回复。