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参数资料
型号： IDT82V3280DQ
厂商： INTEGRATED DEVICE TECHNOLOGY INC
元件分类： 通信及网络
英文描述： WAN PLL
中文描述： SPECIALTY TELECOM CIRCUIT, PQFP100
封装： TQFP-100
文件页数： 20/167页
文件大小： 1039K
代理商： IDT82V3280DQ
IDT82V3280
WAN PLL
Functional Description
20
June 19, 2006
3.3
INPUT CLOCKS & FRAME SYNC SIGNAL
Altogether 14 clocks and 1 frame sync signal are input to the device.
3.3.1
INPUT CLOCKS
The device provides 14 input clock ports.
According to the input port technology, the input ports support the fol-
lowing technologies:
AMI
PECL/LVDS
CMOS
According to the input clock source, the following clock sources are
supported:
T1: Recovered clock from STM-N or OC-n
T2: PDH network synchronization timing
T3: External synchronization reference timing
IN1 and IN2 support the AMI input signal only and the clock source is
from T3. The input clock is a 64 kHz + 8 kHz or 64 kHz + 8 kHz + 0.4
kHz composite clock. The 400HZ_SEL bit should be set to match the
input frequency. Any input violation that does not meet the standard
composite clock structure will induce an AMI violation. The AMI violation
is indicated by the AMI1_VIOL
1
/ AMI2_VIOL
1
bit. If the AMI1_VIOL
2
/
AMI2_VIOL
2
bit is ‘1’, the occurrence of an AMI violation will trigger an
interrupt.
IN3, IN4 and IN7 ~ IN14 support CMOS input signal only and the
clock sources can be from T1, T2 or T3.
IN5 and IN6 support PECL/LVDS input signal only and automatically
detect whether the signal is PECL or LVDS. The clock sources can be
from T1, T2 or T3.
For SDH and SONET networks, the default frequency is different.
SONET / SDH frequency selection is controlled by the IN_SONET_SDH
bit. During reset, the default value of the IN_SONET_SDH bit is deter-
mined by the SONET/
SDH
pin: high for SONET and low for SDH. After
reset, the input signal on the SONET/
SDH
pin takes no effect.
3.3.2
FRAME SYNC INPUT SIGNALS
A 2 kHz, 4 kHz or 8 kHz frame sync signal is input on the EX_SYNC1
pin. It is a CMOS input. The input frequency should match the setting in
the SYNC_FREQ[1:0] bits.
The frame sync input signal is used for frame sync output signal syn-
chronization. Refer to
Chapter 3.13.2 Frame SYNC Output Signals
for
details.
Table 3: Related Bit / Register in Chapter 3.3
Bit
Register
Address (Hex)
400HZ_SEL
IN1_CNFG
IN2_CNFG
14
15
AMI1_VIOL
1
AMI2_VIOL
1
AMI1_VIOL
2
AMI2_VIOL
2
IN_SONET_SDH
SYNC_FREQ[1:0]
INTERRUPT3_STS
0F
INTERRUPTS3_ENABLE_CNFG
12
INPUT_MODE_CNFG
09
相关PDF资料
PDF描述
IDT82V3280DQG WAN PLL
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