参数资料
型号: IDT89HPES16NT2ZBBC
厂商: IDT, Integrated Device Technology Inc
文件页数: 2/29页
文件大小: 0K
描述: IC PCI SW 16LANE 2PORT 484-CABGA
标准包装: 60
系列: PRECISE™
类型: PCI Express 开关 - Gen1
应用: 服务器,储存,通信,嵌入式,消费品
安装类型: 表面贴装
封装/外壳: 484-BGA
供应商设备封装: 484-CABGA(23x23)
包装: 托盘
其它名称: 89HPES16NT2ZBBC
10 of 29
January 5, 2009
IDT 89HPES16NT2 Data Sheet
TRX-EYE-MEDIUM TO
MAX JITTER
Max time between jitter median & max deviation
0.3
UI
TRX-IDLE-DET-DIFF-
ENTER TIME
Unexpected Idle Enter Detect Threshold Integration Time
10
ms
TRX-SKEW
Lane to lane input skew
20
ns
1. Minimum, Typical, and Maximum values meet the requirements under PCI Specification 1.1
Signal
Symbol Reference
Edge
Min Max Unit
Timing
Diagram
Reference
GPIO
GPIO[7:0]1
1. GPIO signals must meet the setup and hold times if they are synchronous or the minimum pulse width if
they are asynchronous.
Tpw_13b2
2. The values for this symbol were determined by calculation, not by testing.
None
50
ns
Table 10 GPIO AC Timing Characteristics
Signal
Symbol
Reference
Edge
Min
Max
Unit
Timing
Diagram
Reference
JTAG
JTAG_TCK
Tper_16a
none
50.0
ns
Thigh_16a,
Tlow_16a
10.0
25.0
ns
JTAG_TMS1,
JTAG_TDI
1. The JTAG specification, IEEE 1149.1, recommends that JTAG_TMS should be held at 1 while the signal applied at JTAG_TRST_N
changes from 0 to 1. Otherwise, a race may occur if JTAG_TRST_N is deasserted (going from low to high) on a rising edge of JTAG_TCK
when JTAG_TMS is low, because the TAP controller might go to either the Run-Test/Idle state or stay in the Test-Logic-Reset state.
Tsu_16b
JTAG_TCK rising
2.4
ns
Thld_16b
1.0
ns
JTAG_TDO
Tdo_16c
JTAG_TCK falling
20
ns
Tdz_16c2
2. The values for this symbol were determined by calculation, not by testing.
—20
ns
JTAG_TRST_N
Tpw_16d2
none
25.0
ns
Table 11 JTAG AC Timing Characteristics
Parameter
Description
Min1
Typical1
Max1
Units
Table 9 PCIe AC Timing Characteristics (Part 2 of 2)
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