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| 型号： | IDTCSP5992-5JRI |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | 时钟及定时 |
| 英文描述： | PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQCC32 |
| 封装： | PLASTIC, LCC-32 |
| 文件页数： | 1/8页 |
| 文件大小： | 123K |
| 代理商： | IDTCSP5992-5JRI |
1
COMMERCIALANDINDUSTRIALTEMPERATURERANGES
IDTCSP5992
PROGRAMMABLESKEWPLLCLOCKDRIVERTURBOCLOCK
GN D /sO E
1Q 0
Sk e w
Se le ct
1Q 1
1F 1:0
3
2Q 0
Sk e w
Se le ct
2Q 1
2F 1:0
FS
3
RE F
PL L
FB
3
3Q 0
Sk e w
Se le ct
3Q 1
3F 1:0
3
4Q 0
4Q 1
Sk e w
Se le ct
4F 1:0
3
V DDQ /P E
FEBRUARY 2000
2000
Integrated Device Technology, Inc.
DSC-5810/-
c
IDTCSP5992
COMMERCIAL/INDUSTRIAL TEMPERATURE RANGES
PROGRAMMABLE SKEW
PLL CLOCK DRIVER
TURBOCLOCK
DESCRIPTION:
The CSP5992 is a high fanout PLL based clock driver intended for
high performance computing and data-communications applications. A
key feature of the programmable skew is the ability of outputs to lead or
lag the REF input signal. The CSP5992 has eight programmable skew
outputs in four banks of 2. Skew is controlled by 3-level input signals
that may be hard-wired to appropriate HIGH-MID-LOW levels.
The CSP5992 maintains Cypress CY7B992 compatibility while pro-
viding two additional features: Synchronous Output Enable (GND/
sOE),
and Positive/Negative Edge Synchronization (VDDQ/PE). When the GND/
sOE pin is held low, all the outputs are synchronously enabled (CY7B992
compatibility). However, if GND/
sOE is held high, all the outputs except
3Q0 and 3Q1 are synchronously disabled.
Furthermore, when the VDDQ/PE is held high, all the outputs are
synchronized with the positive edge of the REF clock input (CY7B992
compatibility). When VDDQ/PE is held low, all the outputs are synchro-
nized with the negative edge of REF.
FEATURES:
4 pairs of programmable skew outputs
Low skew: 200ps same pair, 250ps all outputs
Selectable positive or negative edge synchronization:
Excellent for DSP applications
Synchronous output enable
Output frequency: 6.25MHz to 100MHz
2x, 4x, 1/2, and 1/4 outputs
5V with CMOS outputs
3 skew grades:
CSP5992-2: tSKEW0<250ps
CSP5992-5: tSKEW0<500ps
CSP5992-7: tSKEW0<750ps
3-level inputs for skew and PLL range control
PLL bypass for DC testing
External feedback, internal loop filter
46mA IOLhigh drive outputs
Low Jitter: <200ps peak-to-peak
Outputs drive 50
terminatedlines
Pin-compatible with Cypress CY7B992
Available in PLCC Package
FUNCTIONAL BLOCK DIAGRAM
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