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参数资料
| 型号： | IDTCSPT857CPFI |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | 时钟及定时 |
| 英文描述： | 2.5V - 2.6V PHASE LOCKED LOOP DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER |
| 中文描述： | PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO48 |
| 封装： | TVSOP-48 |
| 文件页数： | 1/15页 |
| 文件大小： | 148K |
| 代理商： | IDTCSPT857CPFI |
1
IDTCSPT857C
2.5V - 2.6V PLL DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
2003 Integrated Device Technology, Inc.
DSC-6201/13
c
IDTCSPT857C
COMMERCIAL AND INDUS T RIAL T EMPERAT URE RANGES
2.5V - 2.6V PHASE LOCKED
LOOP DIFFERENTIAL 1:10
SDRAM CLOCK DRIVER
J UNE 2003
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
FEATURES:
1 to 10 differential clock distribution
Optimized for clock distribution in DDR (Double Data Rate)
SDRAMapplications
Operating frequency: 60MHz to 220MHz
Very low skew:
– <100ps for PC1600 - PC2700
– <75ps for PC3200
Very low jitter:
– <75ps for PC1600 - PC2700
– <50ps for PC3200
2.5V AV
DD
and 2.5V V
DDQ
for PC1600-PC2700
2.6V AV
DD
and 2.6V V
DDQ
for PC3200
CMOS control signal input
Test mode enables buffers while disabling PLL
Low current power-down mode
Tolerant of Spread Spectrum input clock
Available in 48-pin TSSOP and TVSOP, 40-pin VFQFPN, and 56-
pin VFBGA packages
DESCRIPTION:
The CSPT857C is a PLL based clock driver that acts as a zero delay buffer
to distribute one differential clock input pair(CLK,
CLK
) to 10 differential output
pairs (Y
[0:9]
,
Y
[0:9]
) and one differential pair of feedback clock output (FBOUT,
FBOUT
). External feedback pins (FBIN,
FBIN
) for synchronization of the
outputs to the input reference is provided. A CMOS Enable/Disable pin is
available for low power disable. When the input frequency falls below
approximately 20MHz, the device will enter power down mode. In this mode,
the receivers are disabled, the PLL is turned off, and the output clock drivers
are tristated, resulting in a current consumption of less than 200
μ
A.
The CSPT857C requires no external components and has been optimsed
for very low I/O phase error, skew, and jitter, while maintaining frequency and
duty cycle over the operating voltage and temperature range. The CSPT857C,
designed for use in both module assemblies and systemmotherboard based
solutions, provides an optimumhigh-performance clock source.
The CSPT857C is available in Commercial Temperature Range (0
°
C to
+70
°
C) and Industrial Temperature Range (-40
°
C to +85
°
C). See Ordering
Information for details.
APPLICATIONS:
Meets or exceeds JEDEC standard JESD 82-1A for registered
DDR clock driver
Meets proposed DDR1-400 specification
For all DDR1 speeds: PC1600 (DDR200), PC2100 (DDR266),
PC2700 (DDR333), PC3200 (DDR400)
Along with SSTV16857, SSTVF16857, SSTV16859, SSTVM16859,
SSTVF16859, DDR1 register, provides complete solution for
DDR1 DIMMs
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相关代理商/技术参数 |
参数描述 |
|---|---|
| IDTCSPT857D | 制造商:IDT 制造商全称:Integrated Device Technology 功能描述:2.5V - 2.6V PHASE LOCKED LOOP DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER |
| IDTCSPT857DBV | 制造商: 功能描述: 制造商:undefined 功能描述: |
| IDTCSPT857DBVG | 功能描述:IC PLL CLK DVR SDRAM 56-CABGA RoHS:是 类别:集成电路 (IC) >> 时钟/计时 - 专用 系列:- 标准包装:28 系列:- 类型:时钟/频率发生器 PLL:是 主要目的:Intel CPU 服务器 输入:时钟 输出:LVCMOS 电路数:1 比率 - 输入:输出:3:22 差分 - 输入:输出:无/是 频率 - 最大:400MHz 电源电压:3.135 V ~ 3.465 V 工作温度:0°C ~ 85°C 安装类型:表面贴装 封装/外壳:64-TFSOP （0.240"，6.10mm 宽） 供应商设备封装:64-TSSOP 包装:管件 |
| IDTCSPT857DBVG8 | 功能描述:IC PLL CLK DVR SDRAM 56-CABGA RoHS:是 类别:集成电路 (IC) >> 时钟/计时 - 专用 系列:- 标准包装:28 系列:- 类型:时钟/频率发生器 PLL:是 主要目的:Intel CPU 服务器 输入:时钟 输出:LVCMOS 电路数:1 比率 - 输入:输出:3:22 差分 - 输入:输出:无/是 频率 - 最大:400MHz 电源电压:3.135 V ~ 3.465 V 工作温度:0°C ~ 85°C 安装类型:表面贴装 封装/外壳:64-TFSOP （0.240"，6.10mm 宽） 供应商设备封装:64-TSSOP 包装:管件 |
| IDTCSPT857DBVI | 制造商:IDT 制造商全称:Integrated Device Technology 功能描述:2.5V - 2.6V PHASE LOCKED LOOP DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER |
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